Arthur Heymans cd96fed5dc soc/intel/cache_as_ram.S: Add macro to detect bootguard nem ... Change-Id: I3867fce29d23b647fad9845b9a5c08bb949fa354 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55783 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-06-24 09:00:50 +00:00
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amd	soc/amd/common/acp: Populate _WOV ACPI method	2021-06-23 19:19:19 +00:00
cavium
example
intel	soc/intel/cache_as_ram.S: Add macro to detect bootguard nem	2021-06-24 09:00:50 +00:00
mediatek	soc/mediatek/mt8195: Support 4 channel DRAM in DPM init flow	2021-06-24 03:13:53 +00:00
nvidia
qualcomm	sc7280: Add target specific GPIO pin definitions	2021-06-11 07:36:16 +00:00
rockchip
samsung	commonlib/region: Turn addrspace_32bit into a more official API	2021-04-21 02:06:26 +00:00
sifive
ti	soc/ti/am335x/mmc.c: Fix memset length argument	2021-04-04 09:58:26 +00:00
ucb