Kyösti Mälkki cd7a70f487 soc/intel: Use common romstage code ... This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-08-26 21:08:41 +00:00
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core2	cpu/intel/car: Remove unneeded white space	2019-01-17 13:20:43 +00:00
non-evict	cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK	2019-04-21 23:31:26 +00:00
p3	cpu/intel/car: Remove unneeded white space	2019-01-17 13:20:43 +00:00
p4-netburst	coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)	2019-03-08 08:33:24 +00:00
bootblock.c	cpu/intel/car/bootblock.c: Report BIST failures	2019-01-08 15:37:18 +00:00
bootblock.h	cpu/intel/car: Enable use of C_ENVIRONMENT_BOOTBLOCK	2019-01-08 15:35:08 +00:00
romstage.c	soc/intel: Use common romstage code	2019-08-26 21:08:41 +00:00