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from v2 to install them. Linux boots fine and all interrupts seem to work correctly -- the network comes up, USB hot plug works, I can mount the USB disk, etc. To enable pirq tables for a given mainboard, simply add the select PIRQ_TABLE (see below) to the Kconfig for that board. Again, this code builds and boots linux on the alix1c. I think, with this change, we are very close to moving ALL LX boards to v3 and deprecating v2. The major remaining fix is to add an empty LAR entry to fill empty space in LAR and speed up the LAR file search process. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> Index: include/tables.h Add prototype, conditioned on CONFIG_PIRQ_TABLE Index: util/x86emu/vm86.c Comment out 'debug trap' code that scribbles vectors at 0x4000. I don't know why this is here, but I'd like to leave it #if'ed out -- somebody, at some point, thought we needed it. To reenable, we will need to move stage2 code or these magic vectors. Index: arch/x86/Makefile Add support for conditional compilation of pirq support code. Index: arch/x86/pirq_routing.c Add this file from v2. Index: arch/x86/archtables.c Add call to write_pirq_routing_table (controlled by #ifdef CONFIG_PIRQ_TABLE) Index: arch/x86/Kconfig Add new config variable: PIRQ_TABLE Index: device/device.c Fix some trivial bugs. Index: mainboard/pcengines/alix1c/Makefile Add pirq table code for stage2 Index: mainboard/pcengines/alix1c/dts Modify dts to properly set southbridge variables Index: mainboard/pcengines/alix1c/irq_tables.c Add code from v2 for the alix1c. Index: mainboard/pcengines/Kconfig Add 'select PIRQ_TABLE' Index: include/arch/x86/pirq_routing.h Add include file from v2. Remove all the SLOTCOUNT nonsense. This hack was only needed for a very early version of gcc 3.x, where they screwed up the creation of struct members that used the [] syntax for variable-length array at the end of the struct. Index: include/device/pci.h Add prototype git-svn-id: svn://coreboot.org/repository/coreboot-v3@582 f3766cd6-281f-0410-b1cd-43a5c92072e9
255 lines
9.3 KiB
Makefile
255 lines
9.3 KiB
Makefile
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2006-2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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ifeq ($(CONFIG_ARCH_X86),y)
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INITCFLAGS := $(CFLAGS) -I$(src)/include/arch/x86 -I$(src)/include \
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-I$(obj) -fno-builtin
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SILENT := >/dev/null 2>&1
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#
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# Build the ROM Image / LAR archive
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#
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# coreboot v3 is completely modular. One module, the bootblock (stage0),
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# is mandatory. All modules are packed together in a LAR archive.
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# The LAR archive may contain any number of stages, payloads and option ROMs.
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#
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ROM_SIZE := $(shell expr $(CONFIG_COREBOOT_ROMSIZE_KB) \* 1024)
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LARFILES := nocompress:normal/initram normal/stage2 nocompress:normal/option_table
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ifneq ($(CONFIG_PAYLOAD_NONE),y)
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LARFILES += normal/payload
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endif
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DECOMPRESSORS :=
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ifeq ($(CONFIG_COMPRESSION_LZMA),y)
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DECOMPRESSORS += lzma.o
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endif
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ifeq ($(CONFIG_COMPRESSION_NRV2B),y)
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DECOMPRESSORS += nrv2b.o
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endif
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COMPRESSFLAG :=
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ifeq ($(CONFIG_DEFAULT_COMPRESSION_LZMA),y)
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COMPRESSFLAG := -C lzma
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endif
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ifeq ($(CONFIG_DEFAULT_COMPRESSION_NRV2B),y)
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COMPRESSFLAG := -C nrv2b
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endif
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$(obj)/coreboot.rom $(obj)/coreboot.map: $(obj)/coreboot.bootblock $(obj)/util/lar/lar lzma nrv2b $(obj)/coreboot.initram $(obj)/coreboot.stage2 $(obj)/option_table
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$(Q)rm -rf $(obj)/lar.tmp
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$(Q)mkdir $(obj)/lar.tmp
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$(Q)mkdir $(obj)/lar.tmp/normal
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$(Q)cp $(obj)/coreboot.initram $(obj)/lar.tmp/normal/initram
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$(Q)cp $(obj)/coreboot.stage2 $(obj)/lar.tmp/normal/stage2
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$(Q)cp $(obj)/option_table $(obj)/lar.tmp/normal/option_table
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ifeq ($(CONFIG_PAYLOAD_NONE),y)
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$(Q)printf " PAYLOAD none (as specified by user)\n"
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else
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$(Q)# TODO: Print sth. other than $(CONFIG_PAYLOAD_FILE) if compressed.
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$(Q)if [ -r $(CONFIG_PAYLOAD_FILE) ]; then \
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printf " PAYLOAD $(CONFIG_PAYLOAD_FILE)\n"; \
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cp $(CONFIG_PAYLOAD_FILE) $(obj)/lar.tmp/normal/payload; \
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else \
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printf "Error: payload file '$(CONFIG_PAYLOAD_FILE)' not found.\n"; \
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exit 1; \
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fi
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endif
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$(Q)printf " LAR $(subst $(shell pwd)/,,$(@))\n"
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$(Q)rm -f $(obj)/coreboot.rom
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$(Q)cd $(obj)/lar.tmp && ../util/lar/lar $(PARSEELF) $(COMPRESSFLAG) -c \
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../coreboot.rom \
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$(LARFILES) \
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-s $(ROM_SIZE) -b $(obj)/coreboot.bootblock
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$(Q)# QEMU wants bios.bin:
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$(Q)# Run "qemu -L build/ -serial stdio -hda /dev/zero".
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$(Q)printf " CP $(subst $(shell pwd)/,,$(obj)/bios.bin)\n"
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$(Q)cp $@ $(obj)/bios.bin
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$(Q)echo "Coreboot ROM Image:" > $(obj)/coreboot.map
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$(Q)$(obj)/util/lar/lar -l $(obj)/coreboot.rom >> $(obj)/coreboot.map
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$(Q)(echo; echo "Stage 0/1 Map:") >> $(obj)/coreboot.map
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$(Q)cat $(obj)/stage0.init.map >> $(obj)/coreboot.map
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$(Q)(echo; echo "Stage Initram Map:") >> $(obj)/coreboot.map
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$(Q)cat $(obj)/coreboot.initram.map >> $(obj)/coreboot.map
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$(Q)(echo; echo "Stage 2 Map:") >> $(obj)/coreboot.map
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$(Q)cat $(obj)/coreboot.stage2.map >> $(obj)/coreboot.map
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$(obj)/coreboot.bootblock: $(obj)/coreboot.vpd $(obj)/stage0.init
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$(Q)printf " BUILD $(subst $(shell pwd)/,,$(@))\n"
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$(Q)cat $^ > $@
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#
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# Coreboot stage0. This is the coreboot "boot block code".
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# It enables Cache-as-RAM and parses the LAR archive for an
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# initram module and the various stages and payload files.
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#
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STAGE0_LIB_OBJ = uart8250.o mem.o elfboot.o lar.o delay.o vtxprintf.o \
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vsprintf.o console.o string.o $(DECOMPRESSORS)
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STAGE0_ARCH_X86_OBJ = stage1.o serial.o archelfboot.o speaker.o \
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udelay_io.o mc146818rtc.o post_code.o
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ifeq ($(CONFIG_CPU_I586),y)
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STAGE0_CAR_OBJ = stage0_i586.o
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else
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ifeq ($(CONFIG_CPU_AMD_GEODELX),y)
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STAGE0_CAR_OBJ = geodelx/stage0.o
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STAGE0_ARCH_X86_OBJ += geodelx/stage1.o
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STAGE0_ARCH_X86_OBJ += ../../northbridge/amd/geodelx/geodelxinit.o
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else
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STAGE0_CAR_OBJ = stage0_i586.o
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endif
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endif
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# We now parse initram as ELF, so we need PARSEELF enabled unconditionally.
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ifeq ($(CONFIG_PAYLOAD_PREPARSE_ELF), y)
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PARSEELF = -e
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else
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PARSEELF = -e
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endif
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STAGE0_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE0_LIB_OBJ)) \
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$(patsubst %,$(obj)/arch/x86/%,$(STAGE0_ARCH_X86_OBJ)) \
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$(patsubst %,$(obj)/arch/x86/%,$(STAGE0_CAR_OBJ)) \
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$(STAGE0_MAINBOARD_OBJ) $(STAGE0_CHIPSET_OBJ)
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$(obj)/stage0.o $(obj)/stage0.init $(obj)/stage0-prefixed.o: $(STAGE0_OBJ)
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$(Q)# We need to be careful. If stage0.o gets bigger than
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$(Q)# 0x4000 - 0x100, we will end up with a 4 gig file.
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$(Q)# I wonder if that behavior is on purpose.
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$(Q)# Note: we invoke gcc (instead of ld directly) here, as we hit
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$(Q)# strange problems in the past. It seems that only gcc knows how
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$(Q)# to properly invoke ld.
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(CC) -nostdlib -static -T $(src)/arch/x86/ldscript.ld \
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$(STAGE0_OBJ) -o $(obj)/stage0.o
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$(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(OBJCOPY) -O binary $(obj)/stage0.o $(obj)/stage0.init
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$(Q)# Do another OBJCOPY to get a copy with renamed symbols
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$(Q)# for XIP code.
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$(Q)printf " OBJCOPY $(subst $(shell pwd)/,,$(@)) (prefixing stage0)\n"
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$(Q)$(OBJCOPY) --prefix-symbols=stage0_ $(obj)/stage0.o $(obj)/stage0-prefixed.o
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$(Q)printf " TEST $(subst $(shell pwd)/,,$(@))\n"
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$(Q)test `wc -c < $(obj)/stage0.init` -gt 20224 && \
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printf "Error. Bootblock got too big.\n" || true
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$(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(NM) $(obj)/stage0.o | sort -u > $(obj)/stage0.init.map
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#
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# This is the rest of coreboot (v2: coreboot_ram.rom).
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# Is this maybe platform independent, except for the "drivers"?
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# Where should it be built, maybe in device/?
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#
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# TODO: This should be compressed with the default compressor.
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#
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STAGE2_LIB_OBJ = stage2.o clog2.o mem.o tables.o delay.o \
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compute_ip_checksum.o string.o
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STAGE2_ARCH_X86_OBJ = archtables.o coreboot_table.o udelay_io.o
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STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o
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STAGE2_ARCH_X86_OBJ += keyboard.o i8259.o isa-dma.o
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ifeq ($(CONFIG_PIRQ_TABLE),y)
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STAGE2_ARCH_X86_OBJ += pirq_routing.o
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endif
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STAGE2_DYNAMIC_OBJ = statictree.o
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STAGE2_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE2_LIB_OBJ)) \
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$(patsubst %,$(obj)/arch/x86/%,$(STAGE2_ARCH_X86_OBJ)) \
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$(patsubst %,$(obj)/device/%,$(STAGE2_DEVICE_OBJ)) \
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$(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_OBJ)) \
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$(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
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STAGE2_OBJ += $(STAGE2_CHIPSET_OBJ)
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ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y)
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ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y)
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# x86emu wants libgcc
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ifneq ($(strip $(CC)),)
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LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
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endif
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endif
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STAGE2_OBJ += $(obj)/util/x86emu/libx86emu.a $(LIBGCC_FILE_NAME)
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endif
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# To reduce code duplication, always make sure STAGE2_OBJ does not contain
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# any object from STAGE0_OBJ.
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STAGE2_OBJ_NEEDED = $(filter-out $(STAGE0_OBJ), $(STAGE2_OBJ))
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$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.init $(STAGE2_OBJ_NEEDED)
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$(Q)# leave a .o with full symbols in it for debugging.
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$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x2000 --entry=stage2 \
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-o $(obj)/coreboot.stage2 $(STAGE2_OBJ_NEEDED)
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$(Q)$(NM) $(obj)/coreboot.stage2 | sort -u > $(obj)/coreboot.stage2.map
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#
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# Build rules.
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#
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$(obj)/arch/x86/%.o: $(src)/arch/x86/%.c
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$(Q)mkdir -p $(dir $@)
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
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# Building asm stub.
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$(obj)/arch/x86/stage0%.o: $(src)/arch/x86/stage0%.S
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(CC) -E $(COREBOOTINCLUDE) $< \
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-o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \
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-DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
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$(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
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$(obj)/arch/x86/geodelx/stage0.o: $(src)/arch/x86/geodelx/stage0.S
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$(Q)mkdir -p $(dir $@)
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(CC) -E $(COREBOOTINCLUDE) $< \
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-o $(obj)/arch/x86/stage0_asm.s -DBOOTBLK=0x1f00 \
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-DRESRVED=0xf0 -DDATE=\"`date +%Y/%m/%d`\"
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$(Q)printf " AS $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
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$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ)
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$(Q)printf " CC $(subst $(shell pwd)/,,$(@)) (XIP)\n"
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$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/coreboot.initram_partiallylinked.o
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$(Q)# initram links against stage0
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$(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \
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$(obj)/coreboot.initram_partiallylinked.o -o $(obj)/coreboot.initram
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$(Q)printf " NM $(subst $(shell pwd)/,,$(@))\n"
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$(Q)$(NM) $(obj)/coreboot.initram | sort -u > $(obj)/coreboot.initram.map
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endif
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