Subrata Banik 56ab8e2aae soc/intel/common/cpu: Use SoC overrides to get CPU privilege level ... This patch implements a SoC overrides to check CPU privilege level as the MSR is not consistent across platforms. For example: On APL/GLK/DNV, it's MSR 0x120 and CNL onwards it's MSR 0x151. BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I515f0a3548bc5d6250e30f963d46f28f3c1b90b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>		2022-01-19 09:57:47 +00:00
..
acpi	soc/intel/tigerlake: Add config option for S3 ACPI	2021-11-15 04:37:44 +00:00
bootblock	soc/tigerlake: Make IO decode / enable register configurable	2021-10-01 18:53:28 +00:00
include/soc	soc/intel/common/cpu: Use SoC overrides to get CPU privilege level	2022-01-19 09:57:47 +00:00
romstage	soc/intel/tigerlake: Hook up SMBus device to devicetree	2021-12-09 21:52:13 +00:00
acpi.c	soc/intel: Remove unused <string.h>	2022-01-05 17:37:49 +00:00
chip.c	soc/intel/tgl: deduplicate the PCIe root port map	2022-01-14 00:29:28 +00:00
chip.h	soc/intel/tgl: Replace dt HeciEnabled by HECI1 disable config	2022-01-14 00:33:14 +00:00
chipset.cb	mb/*/{tglrvp,volteer,deltaur}: move cpu_cluster configuration to chipset.cb	2021-08-16 15:01:11 +00:00
chipset_pch_h.cb	soc/intel/tigerlake: Add PCH-H chipset devicetree	2021-08-24 14:46:16 +00:00
cpu.c	soc/intel/common/cpu: Use SoC overrides to get CPU privilege level	2022-01-19 09:57:47 +00:00
crashlog_lib.c	src/soc/intel: Remove unused <delay.h>	2022-01-05 17:42:01 +00:00
dptf.c	dptf: Move platform-specific information to struct dptf_platform_info	2021-04-13 08:22:49 +00:00
elog.c	src: Drop duplicated includes	2022-01-01 14:55:51 +00:00
espi.c	src: Match array format in function declarations and definitions	2021-05-13 18:34:38 +00:00
finalize.c	soc/intel/{adl,ehl,jsl,tgl}: Remove unused header thermal.h	2021-11-22 08:02:48 +00:00
fsp_params.c	soc/intel/tigerlake: add devicetree option PcieRpSlotImplemented	2022-01-14 00:29:38 +00:00
gpio.c	soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registers	2021-09-23 06:31:48 +00:00
gpio_pch_h.c	soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registers	2021-09-23 06:31:48 +00:00
graphics.c	soc/intel/tigerlake: Hook up GMA ACPI brightness controls	2021-10-07 11:04:48 +00:00
gspi.c
i2c.c
Kconfig	soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entries	2022-01-09 01:47:22 +00:00
lockdown.c
lpm.c	soc/intel/tigerlake: Move LPM functions to new file	2021-09-10 21:53:48 +00:00
Makefile.inc	soc/intel/tigerlake: Implement function to map physical port to EC port	2022-01-12 16:09:47 +00:00
me.c	soc/intel/{adl,ehl,tgl}: Rename spi_protection_mode to mfg_mode	2022-01-02 12:29:07 +00:00
meminit.c	soc/intel/tigerlake: Hook up FSP repository	2021-06-10 05:34:52 +00:00
p2sb.c
pcie_rp.c	soc/intel/tgl/pcie_rp: add TGL-H support	2022-01-14 00:29:13 +00:00
pmc.c	soc/intel: implement ACPI timer disabling per SoC and drop common code	2021-10-17 13:57:53 +00:00
pmutil.c	soc/intel/tigerlake: Clear RTC_BATTERY_DEAD	2021-09-20 15:44:07 +00:00
reset.c
retimer.c	soc/intel/tigerlake: Implement function to map physical port to EC port	2022-01-12 16:09:47 +00:00
smihandler.c	soc/intel/tgl: Replace dt HeciEnabled by HECI1 disable config	2022-01-14 00:33:14 +00:00
soundwire.c	soc/intel/common: Move PMC EPOC related code to Intel common code	2021-06-30 07:34:44 +00:00
spi.c	soc/intel: Update api name for getting spi destination id	2021-10-26 18:12:17 +00:00
systemagent.c	Rename ECAM-specific MMCONF Kconfigs	2021-11-10 17:24:16 +00:00
uart.c	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
xhci.c