coreboot/src
Subrata Banik cc4ca5ec94 mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MB
This patch updates the MTLRVP debug flash layout to optimize WP_RO to 4MB.

Changes for chromeos.fmd:

SI_BIOS:
    RW_SECTION_A/B: Increase to 7.5MB.
    RW_LEGACY: Introduce with 1MB.
    RW_MISC: Increased to 1MB.
    RW_UNUSED: 2MB (reserved)
    WP_RO: Reduce to 4MB

Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the
SPI Flash.

BUG=b:277143384
TEST=Able to build and boot intel/mtlrvp with FSP release and debug image.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie635e3cce1c3fd771e6a17e4b3c1bd700f4729bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-11 11:39:14 +00:00
..
acpi
arch
commonlib
console
cpu
device
drivers
ec ec/lenovo/pmh7/chip.h: Use 'bool' instead of 'int' 2023-04-08 03:36:07 +00:00
include
lib
mainboard mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MB 2023-04-11 11:39:14 +00:00
northbridge
sbom
security security/tpm: make usage of PCRs configurable via Kconfig 2023-04-10 04:01:08 +00:00
soc soc/intel/{adl, cmn}: Send CSE EOP Async CMD early 2023-04-11 11:37:38 +00:00
southbridge sb/intel/i82801gx/chip.h: Use 'bool' instead of 'int' 2023-04-08 03:35:39 +00:00
superio
vendorcode
Kconfig