Arthur Heymans cbc609957f soc/intel/xeon_sp/cpx: Rename FSP UPDs using CPP ... coreboot expects different names for FSP UPDs so use some CPP to make it happy. Change-Id: I4b2c2dd6ba40cb58bc2089eb9204fd4f70b037aa Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>		2021-09-23 06:37:38 +00:00
..
alderlake	mb/google/brya: Migrate brya to use SPD files under spd/	2021-09-23 06:22:27 +00:00
apollolake	vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main	2021-09-16 23:44:20 +00:00
baytrail	cpu/x86/tsc: Deduplicate Makefile logic	2021-09-08 14:35:16 +00:00
braswell	cpu/x86/tsc: Deduplicate Makefile logic	2021-09-08 14:35:16 +00:00
broadwell	soc/broadwell/acpi.c: Fix unresolvable symbol '\DNVS'	2021-09-15 15:28:57 +00:00
cannonlake	soc/intel/cannonlake: Switch to runtime generation of Intel Power Engine	2021-09-10 21:57:20 +00:00
common	soc/intel/{common,tgl,adl}: guard TME Kconfig option by SoC support	2021-09-20 12:19:39 +00:00
denverton_ns	cpu/x86/tsc: Deduplicate Makefile logic	2021-09-08 14:35:16 +00:00
elkhartlake	soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registers	2021-09-23 06:31:48 +00:00
icelake	soc/intel/icelake: correct wrong gpio SMI register base offsets	2021-09-23 06:31:58 +00:00
jasperlake	soc/intel/{xeon-sp,icl,tgl,jsl,ehl}: add NMI_{EN,STS} registers	2021-09-23 06:31:48 +00:00
quark	cpu/x86/tsc: Deduplicate Makefile logic	2021-09-08 14:35:16 +00:00
skylake	vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main	2021-09-16 23:44:20 +00:00
tigerlake	soc/intel/tgl: correct wrong gpio GPI enable register base offset	2021-09-23 06:32:11 +00:00
xeon_sp	soc/intel/xeon_sp/cpx: Rename FSP UPDs using CPP	2021-09-23 06:37:38 +00:00
Kconfig