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Kyösti Mälkki 107f72e674 Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR 
This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be
set with values that are not power of 2. The region programmed
as WB cacheable will include all of ROM_SIZE.

Side-effects to consider:

Memory region below flash may be tagged WRPROT cacheable. As an
example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB.
Since this can overlap CAR, we add an explicit test and fail
on compile should this happen. To work around this problem, one
needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and
define a smaller region for WB cache.

With this change flash regions outside CBFS are also tagged WRPROT
cacheable. This covers IFD and ME and sections ChromeOS may use.

Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4625
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-15 15:26:48 +01:00
..
a-trend
aaeon AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c" 2013-06-04 17:56:48 +02:00
abit
adlink
advansus AMD fam10: Drop RAMINIT_SYSINFO 2013-12-29 19:45:41 +01:00
advantech
amd Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR 2014-01-15 15:26:48 +01:00
aopen usbdebug: Quirk for board aopen/dxplplusu 2013-06-12 05:22:46 +02:00
arima AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includes 2013-12-26 23:22:17 +01:00
artecgroup AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c" 2013-06-04 17:56:48 +02:00
asi
asrock Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR 2014-01-15 15:26:48 +01:00
asus Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR 2014-01-15 15:26:48 +01:00
avalue AMD fam10: Drop RAMINIT_SYSINFO 2013-12-29 19:45:41 +01:00
axus
azza
bachmann OT200: bring LEDs into a defined state 2013-06-10 08:45:50 +02:00
bcom
bifferos
biostar
broadcom AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includes 2013-12-26 23:22:17 +01:00
compaq
cubietech cubieboard: Setup CPU clock in romstage and load ramstage 2014-01-14 14:15:12 +01:00
digitallogic AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c" 2013-06-04 17:56:48 +02:00
dmp vortex86ex: Cleanup earlymtrr.c include 2013-12-26 23:18:28 +01:00
eaglelion
ecs
emulation armv7: Remove SYS_TEXT_BASE config. 2013-12-20 21:56:20 +01:00
getac smi: Update mainboard_smi_gpi() to have 32bit argument 2013-11-24 07:40:22 +01:00
gigabyte AMD K8 (rev F): Move rev F0/F1 workaround to header 2013-12-30 07:20:38 +01:00
gizmosphere Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR 2014-01-15 15:26:48 +01:00
google ibexpeak / bd82x6x: Make SATA mode user-visible option. 2014-01-12 18:03:23 +01:00
hp AMD K8 (rev F): Move rev F0/F1 workaround to header 2013-12-30 07:20:38 +01:00
ibase Remove PCI_ROM_RUN option 2013-12-24 14:40:49 +01:00
ibm AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includes 2013-12-26 23:22:17 +01:00
iei AMD fam10: Drop RAMINIT_SYSINFO 2013-12-29 19:45:41 +01:00
intel ibexpeak / bd82x6x: Make SATA mode user-visible option. 2014-01-12 18:03:23 +01:00
iwave Move select MMCONF_SUPPORT under northbridge 2013-07-03 19:34:11 +02:00
iwill AMD K8 (pre-F): Clean platforms without K8_REV_F_SUPPORT 2013-12-30 07:15:27 +01:00
jetway AMD fam10: Drop RAMINIT_SYSINFO 2013-12-29 19:45:41 +01:00
kontron ibexpeak / bd82x6x: Make SATA mode user-visible option. 2014-01-12 18:03:23 +01:00
lanner
lenovo X60: Enable WWAN by default. 2014-01-12 18:06:38 +01:00
lippert Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR 2014-01-15 15:26:48 +01:00
mitac
msi AMD K8 (rev F): Move rev F0/F1 workaround to header 2013-12-30 07:20:38 +01:00
nec
newisys AMD K8: Socket implies K8_REV_F_SUPPORT 2013-12-29 00:04:02 +01:00
nokia
nvidia AMD K8 (rev F): Move rev F0/F1 workaround to header 2013-12-30 07:20:38 +01:00
pcengines PC Engines ALIX.1C: Add CMOS defaults. 2013-06-04 21:31:57 +02:00
rca
roda Remove PCI_ROM_RUN option 2013-12-24 14:40:49 +01:00
samsung ibexpeak / bd82x6x: Make SATA mode user-visible option. 2014-01-12 18:03:23 +01:00
siemens AMD K8 (rev-F): Always have RAMINIT_SYSINFO 2013-12-29 19:45:50 +01:00
soyo
sunw AMD K8: Socket implies K8_REV_F_SUPPORT 2013-12-29 00:04:02 +01:00
supermicro Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR 2014-01-15 15:26:48 +01:00
technexion AMD K8 (rev-F): Always have RAMINIT_SYSINFO 2013-12-29 19:45:50 +01:00
technologic
televideo
thomson Remove PCI_ROM_RUN option 2013-12-24 14:40:49 +01:00
ti beaglebone: Stop reinitializing the console in bootblock.c. 2013-09-17 01:00:39 +02:00
traverse AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c" 2013-06-04 17:56:48 +02:00
tyan Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR 2014-01-15 15:26:48 +01:00
via via/epia-m700: Drop RAMINIT_SYSINFO 2013-12-29 19:45:29 +01:00
winent AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includes 2013-12-26 23:22:17 +01:00
wyse
Kconfig mainboard: Add preliminary support for A10-based Cubieboard 2014-01-08 22:54:22 +01:00