96ac0224ab
This ensures that bridge windows allocate enough space to cover SR-IOV BARs. Without this Linux will print messages, these messages may differ depending on the kernel version used. Debian GNU/Linux 12 (kernel 6.1.0-28-amd64): pci 0000:06:00.0: BAR 7: no space for [mem size 0x00200000 64bit pref] pci 0000:06:00.0: BAR 7: failed to assign [mem size 0x00200000 64bit pref] Ubuntu 22.04.5 LTS (kernel 6.8.0-52-generic): pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: can't assign; no space pci 0000:06:00.0: VF BAR 0 [mem size 0x00200000 64bit pref]: failed to assign TEST=Raptorlake-P Change-Id: Ib169efe5a6b998a8342a895f1456a280669c719d Signed-off-by: Stephen Douthit <stephend@silicom-usa.com> Signed-off-by: Harrie Paijmans <hpaijmans@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34620 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
57 lines
1.8 KiB
C
57 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef DEVICE_PCIEXP_H
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#define DEVICE_PCIEXP_H
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/* (c) 2005 Linux Networx GPL see COPYING for details */
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#include <device/pci_def.h>
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enum aspm_type {
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PCIE_ASPM_NONE = 0,
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PCIE_ASPM_L0S = 1,
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PCIE_ASPM_L1 = 2,
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PCIE_ASPM_BOTH = 3,
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};
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#define ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET 16
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#define ASPM_LTR_L12_THRESHOLD_VALUE_MASK (0x3ff << ASPM_LTR_L12_THRESHOLD_VALUE_OFFSET)
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#define ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET 29
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#define ASPM_LTR_L12_THRESHOLD_SCALE_MASK (0x7 << ASPM_LTR_L12_THRESHOLD_SCALE_OFFSET)
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/* Latency tolerance reporting, max non-snoop latency value 3.14ms */
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#define PCIE_LTR_MAX_NO_SNOOP_LATENCY_3146US 0x1003
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/* Latency tolerance reporting, max snoop latency value 3.14ms */
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#define PCIE_LTR_MAX_SNOOP_LATENCY_3146US 0x1003
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void pciexp_dev_read_resources(struct device *dev);
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void pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
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unsigned int max_devfn);
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void pciexp_scan_bridge(struct device *dev);
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extern struct device_operations default_pciexp_ops_bus;
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void pciexp_hotplug_scan_bridge(struct device *dev);
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extern struct device_operations default_pciexp_hotplug_ops_bus;
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unsigned int pciexp_find_extended_cap(const struct device *dev, unsigned int cap,
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unsigned int offset);
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unsigned int pciexp_find_ext_vendor_cap(const struct device *dev, unsigned int cap,
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unsigned int offset);
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static inline bool pciexp_is_downstream_port(int type)
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{
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return type == PCI_EXP_TYPE_ROOT_PORT ||
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type == PCI_EXP_TYPE_DOWNSTREAM ||
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type == PCI_EXP_TYPE_PCIE_BRIDGE;
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}
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bool pciexp_dev_is_slot_hot_plug_cap(struct device *dev);
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struct device *pcie_find_dsn(const uint64_t serial, const uint16_t vid,
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struct device *from);
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bool pciexp_get_ltr_max_latencies(struct device *dev, u16 *max_snoop, u16 *max_nosnoop);
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#endif /* DEVICE_PCIEXP_H */
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