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coreboot/src/soc
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Stefan Reinauer ca7794854c tegra132: adjust vboot2 memlayout to make coreboot compile 
romstage didn't fit in it's region anymore.

Change-Id: I5a2f41cb0e0a87339dbf61906ee2060e132cc394
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/10759
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2015-07-01 23:37:11 +02:00
..
broadcom/cygnus Remove obsolete EARLY_CONSOLE usage 2015-06-21 21:11:04 +02:00
imgtec/pistachio Remove address from GPLv2 headers 2015-06-24 07:09:24 +02:00
intel soc/intel/common: Restrict common romstage/ramstage code to FSP 2015-06-26 00:01:57 +02:00
marvell/bg4cd Remove obsolete EARLY_CONSOLE usage 2015-06-21 21:11:04 +02:00
nvidia tegra132: adjust vboot2 memlayout to make coreboot compile 2015-07-01 23:37:11 +02:00
qualcomm/ipq806x qualcomm/ipq806x: Fix uart in verstage 2015-06-30 08:18:22 +02:00
rockchip/rk3288 rockchip/rk3288: Initialize CPU in bootblock 2015-07-01 21:43:39 +02:00
samsung Remove empty lines at end of file 2015-06-08 00:55:07 +02:00
ucb/riscv Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00