coreboot/src
Zheng Bao ca6e1f6c04 AMD S3: Program the flash in a bigger data packet
According to spi.c in src/southbridge/amd/agesa/hudson
readwrite = (bytesin + readoffby1) << 4 | bytesout;
We can see that Hudson limits the SPI programming data
packet size as 15.

We used to write data to SPI in dword mode. It didn't
take full advantage of the data packet size. We need to
leverage that to speed up programming time.

Change-Id: I615e3c8e754e58702247bc26cfffbedaf5827ea8
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2306
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-02-18 09:00:24 +01:00
..
arch armv7/exynos5250: fix usage of _stack and _estack 2013-02-16 00:39:01 +01:00
console console: Fix using CMOS for options 2013-02-08 10:00:12 +01:00
cpu AMD S3: Program the flash in a bigger data packet 2013-02-18 09:00:24 +01:00
device sconfig: rename lapic_cluster -> cpu_cluster 2013-02-14 07:07:20 +01:00
drivers spi.h: Rename the spi.h to spi-generic.h 2013-02-11 21:01:47 +01:00
ec Add support for "Butterfly" Chromebook 2013-02-11 22:02:32 +01:00
include AMD Family12h: Fix warnings 2013-02-18 05:01:53 +01:00
lib fix an error message in checkstack() 2013-02-12 05:05:39 +01:00
mainboard OT200: add CMOS support 2013-02-15 09:04:30 +01:00
northbridge AMD Family12h: Fix warnings 2013-02-18 05:01:53 +01:00
southbridge AMD S3: Fix typo vol*a*tile in southbridge Kconfig 2013-02-18 08:59:47 +01:00
superio Remove assembly coded log2 function 2012-11-28 07:57:17 +01:00
vendorcode AMD Family12h: Fix warnings 2013-02-18 05:01:53 +01:00
Kconfig ARMv7: drop multiboot support 2013-02-14 23:55:34 +01:00