Nico Huber a23c5b979d UPSTREAM: mainboard: Clean up boot_option/reboot_bits in cmos.layout ... Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). BUG=None BRANCH=None TEST=None Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Reviewed-on: https://chromium-review.googlesource.com/371504 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org>		2016-08-17 12:49:03 -07:00
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acpi	UPSTREAM: Add newlines at the end of all coreboot files	2016-08-05 11:45:17 -07:00
acpi_tables.c
board_info.txt
cmos.layout	UPSTREAM: mainboard: Clean up boot_option/reboot_bits in cmos.layout	2016-08-17 12:49:03 -07:00
devicetree.cb
dsdt.asl
gpio.h
Kconfig
Kconfig.name
mainboard.c
mainboard_smi.c	UPSTREAM: mainboards: align on using ACPI_Sx definitions	2016-07-15 08:39:45 -07:00
romstage.c
thermal.h