coreboot/src
Elyes HAOUAS c98f2eacfc sb/intel/common/{madt,rcba_pirq}.c: Convert to 96 characters line length
Change-Id: I62a213013d9008d8a4a22b5908b7fc7d1b663c4b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01 06:11:58 +00:00
..
acpi
arch arch/x86/acpigen: Constify fieldlist parameter to acpigen_write_field 2020-04-29 08:44:00 +00:00
commonlib rules.h: Rename ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE 2020-04-23 01:21:56 +00:00
console drivers/pc80/rtc: Drop CMOS_POST_EXTRA option 2020-04-20 06:13:39 +00:00
cpu src: Remove unused 'include <cpu/x86/cache.h>' 2020-05-01 06:10:49 +00:00
device device: Constify struct device * parameter to acpi_fill_ssdt() 2020-04-28 19:50:26 +00:00
drivers src: Remove unused 'include <cpu/x86/cache.h>' 2020-05-01 06:10:49 +00:00
ec device: Constify struct device * parameter to acpi_fill_ssdt() 2020-04-28 19:50:26 +00:00
include device/pci_id: Add Tiger Lake TCSS device ID 2020-04-29 17:19:26 +00:00
lib rules.h: Rename ENV_VERSTAGE to ENV_SEPARATE_VERSTAGE 2020-04-23 01:21:56 +00:00
mainboard mb/google/dedede: add new variant for wheelie 2020-05-01 06:10:38 +00:00
northbridge src: Remove unused 'include <cpu/x86/cache.h>' 2020-05-01 06:10:49 +00:00
security vboot: Always build secdata functions for romstage 2020-04-28 20:34:07 +00:00
soc src: Remove unused 'include <cpu/x86/cache.h>' 2020-05-01 06:10:49 +00:00
southbridge sb/intel/common/{madt,rcba_pirq}.c: Convert to 96 characters line length 2020-05-01 06:11:58 +00:00
superio superio/aspeed/common: Add early configure functions 2020-04-29 16:06:02 +00:00
vendorcode vc/amd/fsp/picasso: Update UPD files to version 0.0.1-r38 2020-04-28 22:50:24 +00:00
Kconfig src/Kconfig: enable USE_BLOBS by default 2020-04-14 10:03:55 +00:00