Maulik V Vaghela 351f1e68c4 soc/intel/alderlake: Update CPU and IGD Device IDs ... Updated CPU ID and IGD ID for Alder Lake as per EDS. TEST=Code compilation works and coreboot is able to boot and identify new device Ids. Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-05-14 09:03:01 +00:00
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dram	device/dram/ddr3: Drop unused MRS helpers	2021-04-05 13:03:58 +00:00
azalia.h
azalia_device.h	device/azalia_device: Add mainboard hook to program codecs	2021-02-10 07:21:11 +00:00
cardbus.h
device.h	device: Drop unused uma_memory_{base,size} globals	2021-05-10 15:07:55 +00:00
gpio.h
i2c.h
i2c_bus.h
i2c_simple.h
mipi_ids.h	drivers/soundwire/alc1308 : Add ALC1308 soundwire device	2021-02-27 09:41:42 +00:00
mmio.h
path.h
pci.h	pciexp_device: Rewrite LTR configuration	2021-03-15 06:04:38 +00:00
pci_def.h	pciexp_device: Rewrite LTR configuration	2021-03-15 06:04:38 +00:00
pci_ehci.h
pci_ids.h	soc/intel/alderlake: Update CPU and IGD Device IDs	2021-05-14 09:03:01 +00:00
pci_mmio_cfg.h	device/Kconfig: Introduce MMCONF_LENGTH	2021-01-30 23:10:22 +00:00
pci_ops.h	device: Switch pci_dev_is_wake_source to take pci_devfn_t	2021-05-03 16:28:42 +00:00
pci_rom.h
pci_type.h	soc/intel/*: drop UART pad configuration from common code	2021-03-12 08:48:03 +00:00
pciexp.h	device/pciexp_device.c: Remove CPP guarding	2021-03-14 19:27:18 +00:00
pcix.h
pnp.h
pnp_def.h
pnp_ops.h
pnp_type.h
resource.h
smbus.h
smbus_def.h
smbus_host.h
soundwire.h
spi.h
xhci.h