coreboot/src
Shaunak Saha c8ae5995bb soc/apollolake: Set up GPIO_TIER1_SCI_EN properly
Currently we are setting the gpio_tier1_sci in smihandler before
going to S3. But this won't work for S0iX as it happens from Linux
kernel and SMI handler is not involved in that flow. We need to
set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux
kernel before going to sleep checks what values are passed through
ASL as wake events (through _PRW), keeps those enabled only and
clears other bits in gpe0 enable registers. So we need to inform
the kernel to keep gpio_tier_sci also set as these are needed for
any wake event. This patch adds ASL code for sleep button device with
HID id PNP0C0E. We are adding _PRW method for sleep button device
with this patch.

BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
     Also from S0iX system is resuming for WIFI wake.

Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16564
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-15 03:16:46 +02:00
..
acpi src/acpi: Capitalize ACPI and SATA 2016-07-31 19:25:40 +02:00
arch arch/acpi_ivrs.h: Update 8-byte IVRS entry values 2016-09-15 01:43:22 +02:00
commonlib commonlib: move DIV_ROUND macros from nvidia/tegra 2016-09-07 20:52:42 +02:00
console src/console: Add required space before opening parenthesis '(' 2016-08-31 20:06:20 +02:00
cpu cpu/amd/family_10h-family_15h: transition away from device_t 2016-09-13 17:25:13 +02:00
device src/device: Add required space before opening parenthesis '(' 2016-08-28 18:27:52 +02:00
drivers driver/intel/fsp20: move lb_framebuffer function 2016-09-15 01:16:41 +02:00
ec src/ec: Improve code formatting 2016-09-07 13:55:05 +02:00
include arch/arm: Add armv7-r configuration 2016-09-12 19:58:43 +02:00
lib edid: Fix a function signature 2016-09-08 23:19:06 +02:00
mainboard mainboard/bap/ode_e20XX: Change SATA from GEN2 to GEN3 2016-09-15 02:37:37 +02:00
northbridge northbridge/intel/nehalem/gma.c: Improve code formatting 2016-09-15 02:31:56 +02:00
soc soc/apollolake: Set up GPIO_TIER1_SCI_EN properly 2016-09-15 03:16:46 +02:00
southbridge southbridge/sis/sis966/lpc.c: Improve code formatting 2016-09-15 02:31:30 +02:00
superio src/superio: Improve code formatting 2016-09-05 03:07:37 +02:00
vboot vboot: consolidate google_chromeec_early_init() calls 2016-08-25 22:50:17 +02:00
vendorcode vendorcode/skylake: Add FSP header files without any adaptations 2016-09-12 19:54:25 +02:00
Kconfig Kconfig: Relocate DEVICETREE symbol 2016-09-06 22:49:06 +02:00