f3ec5ed555
Because cpu/intel/car/romstage.c assumes a 8KiB stack size when setting up stack guards, and all Slot 1 compatible CPUs have enough L1 cache available for the increase. Adjust DCACHE_RAM_BASE to match. Boot tested on asus/p2b-ls and asus/p3b-f using a 1400MHz Tualeron. The latter actually requires this patch to boot successfully. Change-Id: I5b440e7be4f3149378db88872872012c92049c20 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> |
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| .. | ||
| car | ||
| common | ||
| ep80579 | ||
| fit | ||
| fsp_model_206ax | ||
| fsp_model_406dx | ||
| haswell | ||
| hyperthreading | ||
| microcode | ||
| model_6bx | ||
| model_6dx | ||
| model_6ex | ||
| model_6fx | ||
| model_6xx | ||
| model_65x | ||
| model_67x | ||
| model_68x | ||
| model_69x | ||
| model_106cx | ||
| model_206ax | ||
| model_1067x | ||
| model_2065x | ||
| model_f0x | ||
| model_f1x | ||
| model_f2x | ||
| model_f3x | ||
| model_f4x | ||
| slot_1 | ||
| slot_2 | ||
| smm/gen1 | ||
| socket_441 | ||
| socket_BGA956 | ||
| socket_BGA1284 | ||
| socket_FC_PGA370 | ||
| socket_FCBGA559 | ||
| socket_LGA771 | ||
| socket_LGA775 | ||
| socket_LGA1155 | ||
| socket_mFCBGA479 | ||
| socket_mFCPGA478 | ||
| socket_mPGA478 | ||
| socket_mPGA478MN | ||
| socket_mPGA479M | ||
| socket_mPGA603 | ||
| socket_mPGA604 | ||
| socket_PGA370 | ||
| socket_rPGA988B | ||
| socket_rPGA989 | ||
| speedstep | ||
| thermal_monitoring | ||
| turbo | ||
| Kconfig | ||
| Makefile.inc | ||