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Duncan Laurie c806e4cc59 skylake: Add GPIO macro for configuring inverted APIC input 
Add a GPIO macro that allows a pin to be routed to the APIC with
the input inverted.  This allows a normal interrupt to get used as
a GPE during firmware and still be used as a perhiperal interrupt
in the kernel.

BUG=chrome-os-partner:58666
TEST=boot en eve and use TPM IRQ in firmware and OS

Change-Id: I77f727f749fdd5281ff595a9237fe1e634daba96
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17176
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-28 18:59:46 +02:00
..
broadcom/cygnus soc/broadcom/cygnus/ddr_init.c: Correct typo in POWER ON and POWER OK. 2016-08-31 20:23:34 +02:00
dmp/vortex86ex src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
imgtec/pistachio drivers/uart: Use uart_platform_refclk for all UART models 2016-05-09 18:45:44 +02:00
intel skylake: Add GPIO macro for configuring inverted APIC input 2016-10-28 18:59:46 +02:00
lowrisc/lowrisc riscv: add the lowrisc System On Chip support 2016-10-25 22:31:06 +02:00
marvell marvell/mvmap2315: Compose BOOTBLOCK region 2016-10-21 19:42:23 +02:00
mediatek/mt8173 src/soc: Add required space before opening parenthesis '(' 2016-08-31 20:09:42 +02:00
nvidia Makefiles: update cbfs types from bare numbers to values 2016-09-21 09:36:11 +02:00
qualcomm soc/qualcomm/ipq40xx: Fix GPIO pull up config. 2016-10-07 17:55:19 +02:00
rdc/r8610 rdc/r8610: Move to src/soc 2016-05-05 20:08:58 +02:00
rockchip rockchip/rk3399: reset system if DDR init fails 2016-10-25 17:08:58 +02:00
samsung src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
ucb/riscv soc/ucb/riscv: select BOOTBLOCK_CONSOLE 2016-08-15 18:24:42 +02:00