Various recent x86 SOCs have trouble registering short pulses
generated by the H1 to indicate that it is ready for the next
transaction.
This patch adds an error message to report this condition, which would
greatly reduce the amount of guesswork when troubleshooting new
platforms.
BUG=b:144002424
TEST=tried this code on the Drallion device exhibiting the problem,
observed error messages in the coreboot log;
$ grep IRQ ap.log
Cr50 i2c TPM IRQ timeout!
Cr50 i2c TPM IRQ timeout!
Cr50 i2c TPM IRQ timeout!
Cr50 i2c TPM IRQ timeout!
...
Change-Id: I5f6ee3986bed58e12fd0ec8cecbf35f46c9263c2
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
c7fc199f40