coreboot/src/cpu
Aaron Durbin c7b7a3fb44 UPSTREAM: romstage_handoff: remove code duplication
The same pattern was being used throughout the code base
for initializing the romstage handoff structure. Provide
a helper function to initialize the structure with the S3
resume state then utilize it at all the existing call sites.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17646
Tested-by: build bot (Jenkins)
Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>

Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252
Reviewed-on: https://chromium-review.googlesource.com/416155
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-02 14:22:55 -08:00
..
allwinner UPSTREAM: cpu/allwinner/a10/uart_console.c: Init new serial struct variables 2016-11-29 17:39:12 -08:00
amd UPSTREAM: romstage_handoff: remove code duplication 2016-12-02 14:22:55 -08:00
armltd vboot2: add verstage 2015-01-27 01:41:40 +01:00
dmp UPSTREAM: src/cpu: Improve code formatting 2016-09-07 00:16:15 -07:00
intel UPSTREAM: romstage_handoff: remove code duplication 2016-12-02 14:22:55 -08:00
qemu-power8 cpu/qemu-power8: don't enable it for qemu-x86 2016-02-19 20:03:52 +01:00
qemu-x86 qemu-x86: Enable SMP support 2015-12-08 15:54:27 +01:00
ti UPSTREAM: Kconfig: lay groundwork for not assuming SPI flash boot device 2016-08-19 14:19:51 -07:00
via UPSTREAM: src/cpu: Remove unnecessary whitespace 2016-10-11 14:31:47 -07:00
x86 UPSTREAM: cpu/x86/mtrr: allow temporary MTRR range during coreboot 2016-11-14 19:58:59 -08:00
Kconfig UPSTREAM: Kconfig: Add option for microcode filenames 2016-09-08 17:57:33 -07:00
Makefile.inc UPSTREAM: src/cpu: Fix location for cpu_microcode_blob.bin in COREBOOT CBFS only 2016-10-13 04:31:33 -07:00