b2346a56f1
There is currently a fundamental flaw in the current cpu_info() implementation. It assumes that current stack is CONFIG_STACK_SIZE aligned. This assumption breaks down when performing SMM relocation. The first step in performing SMM relocation is changing the SMBASE. This is accomplished by installing the smmstub at 0x00038000, which is the default SMM entry point. The stub is configured to set up a new stack with the size of 1 KiB (CONFIG_SMM_STUB_STACK_SIZE), and an entry point of smm_do_relocation located in RAMSTAGE RAM. This means that when smm_do_relocation is executed, it is running in SMM with a different sized stack. When cpu_info() gets called it will be using CONFIG_STACK_SIZE to calculate the location of the cpu_info struct. This results in reading random memory. Since cpu_info() has to run in multiple environments, we can't use a compile time constant to locate the cpu_info struct. This CL introduces a new way of locating cpu_info. It uses a per-cpu segment descriptor that points to a per-cpu segment that is allocated on the stack. By using a segment descriptor to point to the per-cpu data, we no longer need to calculate the location of the cpu_info struct. This has the following advantages: * Stacks no longer need to be CONFIG_STACK_SIZE aligned. * Accessing an unconfigured segment will result in an exception. This ensures no one can call cpu_info() from an unsupported environment. * Segment selectors are cleared when entering SMM and restored when leaving SMM. * There is a 1:1 mapping between cpu and cpu_info. When using COOP_MULTITASKING, a new cpu_info is currently allocated at the top of each thread's stack. This no longer needs to happen. This CL guards most of the code with CONFIG(CPU_INFO_V2). I did this so reviewers can feel more comfortable knowing most of the CL is a no-op. I would eventually like to remove most of the guards though. This CL does not touch the LEGACY_SMP_INIT code path. I don't have any way of testing it. The %gs segment was chosen over the %fs segment because it's what the linux kernel uses for per-cpu data in x86_64 mode. BUG=b:194391185, b:179699789 TEST=Boot guybrush with CPU_INFO_V2 and verify BSP and APs have correct %gs segment. Verify cpu_info looks sane. Verify booting to the OS works correctly with COOP_MULTITASKING enabled. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I79dce9597cb784acb39a96897fb3c2f2973bfd98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Peers <epeers@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
203 lines
4.4 KiB
Text
203 lines
4.4 KiB
Text
config PARALLEL_MP
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def_bool y
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depends on !LEGACY_SMP_INIT
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depends on SMP
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help
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This option uses common MP infrastructure for bringing up APs
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in parallel. It additionally provides a more flexible mechanism
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for sequencing the steps of bringing up the APs.
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config PARALLEL_MP_AP_WORK
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def_bool n
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depends on PARALLEL_MP
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help
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Allow APs to do other work after initialization instead of going
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to sleep.
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config LEGACY_SMP_INIT
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bool
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choice LAPIC_ACCESS_MODE
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prompt "APIC operation mode"
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default XAPIC_ONLY
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config XAPIC_ONLY
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prompt "Set XAPIC mode"
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bool
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config X2APIC_ONLY
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prompt "Set X2APIC mode"
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bool
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depends on PARALLEL_MP
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config X2APIC_RUNTIME
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prompt "Support both XAPIC and X2APIC"
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bool
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depends on PARALLEL_MP
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endchoice
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config UDELAY_LAPIC
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bool
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default n
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config LAPIC_MONOTONIC_TIMER
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def_bool n
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depends on UDELAY_LAPIC
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help
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Expose monotonic time using the local APIC.
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config UDELAY_LAPIC_FIXED_FSB
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int
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config UDELAY_TSC
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bool
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default n
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config UNKNOWN_TSC_RATE
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bool
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default y if LAPIC_MONOTONIC_TIMER
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config TSC_MONOTONIC_TIMER
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def_bool n
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depends on UDELAY_TSC
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help
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Expose monotonic time using the TSC.
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config TSC_SYNC_LFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an lfence instruction in order to synchronize
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rdtsc. This is true for all modern AMD CPUs.
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config TSC_SYNC_MFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an mfence instruction in order to synchronize
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rdtsc. This is true for all modern Intel CPUs.
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config SETUP_XIP_CACHE
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bool
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depends on !NO_XIP_EARLY_STAGES
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help
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Select this option to set up an MTRR to cache XIP stages loaded
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from the bootblock. This is useful on platforms lacking a
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non-eviction mode and therefore need to be careful to avoid
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eviction.
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config CPU_ADDR_BITS
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int
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default 36
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config LOGICAL_CPUS
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bool
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default y
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config HAVE_SMI_HANDLER
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bool
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default n
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depends on (SMM_ASEG || SMM_TSEG)
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config NO_SMM
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bool
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default n
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config SMM_ASEG
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bool
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default n
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depends on !NO_SMM
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config SMM_TSEG
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bool
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default y
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depends on !(NO_SMM || SMM_ASEG)
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if SMM_TSEG
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config SMM_MODULE_HEAP_SIZE
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hex
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default 0x4000
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help
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This option determines the size of the heap within the SMM handler
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modules.
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config SMM_MODULE_STACK_SIZE
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hex
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default 0x800 if ARCH_RAMSTAGE_X86_64
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default 0x400
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help
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This option determines the size of the stack within the SMM handler
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modules.
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config SMM_STUB_STACK_SIZE
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hex
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default 0x400
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help
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This option determines the size of the stack within the SMM handler
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modules.
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endif
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config SMM_LAPIC_REMAP_MITIGATION
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bool
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default y if NORTHBRIDGE_INTEL_I945
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default y if NORTHBRIDGE_INTEL_GM45
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default y if NORTHBRIDGE_INTEL_IRONLAKE
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default n
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config SERIALIZED_SMM_INITIALIZATION
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bool
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default n
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help
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On some CPUs, there is a race condition in SMM.
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This can occur when both hyperthreads change SMM state
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variables in parallel without coordination.
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Setting this option serializes the SMM initialization
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to avoid an ugly hang in the boot process at the cost
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of a slightly longer boot time.
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config X86_AMD_FIXED_MTRRS
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bool
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default n
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help
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This option informs the MTRR code to use the RdMem and WrMem fields
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in the fixed MTRR MSRs.
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config X86_AMD_INIT_SIPI
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bool
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default n
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help
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This option limits the number of SIPI signals sent during during the
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common AP setup. Intel documentation specifies an INIT SIPI SIPI
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sequence, however this doesn't work on some AMD platforms. These
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newer AMD platforms don't need the 10ms wait between INIT and SIPI,
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so skip that too to save some time.
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config SOC_SETS_MSRS
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bool
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default n
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help
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The SoC requires different access methods for reading and writing
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the MSRs. Use SoC specific routines to handle the MSR access.
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config RESERVE_MTRRS_FOR_OS
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bool
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default n
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help
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This option allows a platform to reserve 2 MTRRs for the OS usage.
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The Intel SDM documents that the the first 6 MTRRs are intended for
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the system BIOS and the last 2 are to be reserved for OS usage.
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However, modern OSes use PAT to control cacheability instead of
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using MTRRs.
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config CPU_INFO_V2
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bool
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depends on PARALLEL_MP
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help
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Enables the new method of locating struct cpu_info. This new method
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uses the %gs segment to locate the cpu_info pointer. The old method
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relied on the stack being CONFIG_STACK_SIZE aligned.
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