Jonathan Neuschäfer ae91cdabf6 arch/riscv: Advance the PC after handling misaligned load/store ... After emulating an instruction in the misaligned load/store handler, we need to increment the program counter by the size of instruction. Otherwise the same instruction is executed (and emulated) again and again. While were at it: Also return early in the unlikely case that the faulting instruction is not 16 or 32 bits long, and be more explicit about the return values of fetch_*bit_instruction. Tested by Philipp Hug, using the linuxcheck payload. Fixes: cda59b56ba ("riscv: update misaligned memory access exception handling") Change-Id: Ie2dc0083835809971143cd6ab89fe4f7acd2a845 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2018-09-26 18:52:08 +00:00
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arm	arch/arm/include/armv7/arch: Remove dead code	2018-09-19 10:35:09 +00:00
arm64	complier.h: add __always_inline and use it in code base	2018-09-14 08:16:37 +00:00
mips	arch/{mips,power8}/include/arch: Don't use device_t	2018-09-21 14:12:18 +00:00
power8	arch/{mips,power8}/include/arch: Don't use device_t	2018-09-21 14:12:18 +00:00
riscv	arch/riscv: Advance the PC after handling misaligned load/store	2018-09-26 18:52:08 +00:00
x86	acpi: Call acpi_gen_writeSTA by status from device tree	2018-09-16 08:37:42 +00:00