Frans Hendriks c6d672fe1d src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area ... Calculation of memory reserved by FSP is incorrect. Use CBMEM_ID_FSP_RESERVED_MEMORY to determine the memory area BUG=N/A TEST=Intel CherryHill CRB Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/29333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>		2019-02-28 17:09:29 +00:00
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apollolake	soc/intel: Add mem_rank info in SMBIOS	2019-02-18 20:25:42 +00:00
baytrail	intel/spi: Switch to native PCI config accessors	2019-02-28 10:34:43 +00:00
braswell	src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area	2019-02-28 17:09:29 +00:00
broadwell	intel/spi: Switch to native PCI config accessors	2019-02-28 10:34:43 +00:00
cannonlake	soc/intel/cannonlake: Add CometLake SoC support	2019-02-28 17:08:27 +00:00
common	soc/intel/cannonlake: Add Comet Lake U SA 2+2 Device ID	2019-02-28 02:22:11 +00:00
denverton_ns	soc/intel/denverton_ns: Add ACPI T-States and P-States	2019-01-28 13:33:30 +00:00
fsp_baytrail	intel/spi: Switch to native PCI config accessors	2019-02-28 10:34:43 +00:00
fsp_broadwell_de	security/vboot: Add measured boot mode	2019-02-25 22:29:16 +00:00
icelake	soc/intel: Add mem_rank info in SMBIOS	2019-02-18 20:25:42 +00:00
quark	console: Split loglevel for fast and slow	2019-02-27 11:10:00 +00:00
skylake	soc/intel/skylake: Remove redundant PM emulation timer macros	2019-02-28 02:21:44 +00:00
Kconfig	src/cpu: Remove dead sourced lines	2018-11-15 10:25:20 +00:00