Wonkyu Kim c66c15334a soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD ... This patch adds support for enabling/disabling PCIe hot-plug via a chip config option PcieRpHotPlug, which is copied to the corresponding FSP-S UPD. BUG=b:156879564 BRANCH=none TEST=Boot Volteer/RVP with FSP log and check hotplug enabled/disabled Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I4c0187644b6ca9735f1b159e110e3466af14ff71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41794 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-06-17 09:18:45 +00:00
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apollolake	soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)	2020-06-16 08:03:44 +00:00
baytrail	sb,soc/intel: Replace smm_southbridge_enable_smi()	2020-06-16 08:04:09 +00:00
braswell	sb,soc/intel: Replace smm_southbridge_enable_smi()	2020-06-16 08:04:09 +00:00
broadwell	sb,soc/intel: Replace smm_southbridge_enable_smi()	2020-06-16 08:04:09 +00:00
cannonlake	soc/intel/cannonlake/vr_config: Add CFL defaults to TDC powerlimit	2020-06-17 09:17:47 +00:00
common	cpu/x86: Define MTRR_CAP_PRMRR	2020-06-16 08:05:16 +00:00
denverton_ns	sb,soc/intel: Replace smm_southbridge_enable_smi()	2020-06-16 08:04:09 +00:00
icelake	soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)	2020-06-16 08:03:44 +00:00
jasperlake	soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)	2020-06-16 08:03:44 +00:00
quark	ACPI: Remove Kconfig COMMON_FADT	2020-06-10 12:53:08 +00:00
skylake	cpu/x86: Define MTRR_CAP_PRMRR	2020-06-16 08:05:16 +00:00
tigerlake	soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD	2020-06-17 09:18:45 +00:00
xeon_sp	sb,soc/intel: Replace smm_southbridge_enable_smi()	2020-06-16 08:04:09 +00:00
Kconfig