coreboot/src
Ronak Kanabar c4813ea260 vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00
The headers added are generated as per FSP v2162_00.
Previous FSP version was v2117_00.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Remove DisableDimmMc*Ch* Upds in FspmUpd.h
- Add DisableMc*Ch* Upds in FspmUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h

Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid
compilation failure other change related to UPDs name change will be
part of next patch in relation chain.

BUG=b:187189546
BRANCH=None
TEST=Build and boot ADLRVP using all the patch in relation chain.

Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e
Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913
Cq-Depend: chromium:TODO
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54083
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16 22:17:26 +00:00
..
acpi src/acpi: Add initial support for HMAT 2021-05-14 08:56:59 +00:00
arch cbfs: Increase mcache size defaults 2021-05-14 00:35:46 +00:00
commonlib
console src: Retype option API to use unsigned integers 2021-05-06 14:48:15 +00:00
cpu cpu/amd/pi/00730F01/model_16_init.c: create correct MTRR solution 2021-05-13 17:18:42 +00:00
device device/device.c: Print bus numbers in decimal 2021-05-11 12:52:30 +00:00
drivers drivers/i2c/cs42l42: Make HS_BIAS_SENSE_EN optional 2021-05-12 08:00:12 +00:00
ec src: Retype option API to use unsigned integers 2021-05-06 14:48:15 +00:00
include soc/intel/alderlake: Update CPU and IGD Device IDs 2021-05-14 09:03:01 +00:00
lib cbfs: Increase mcache size defaults 2021-05-14 00:35:46 +00:00
mainboard mb/google/mancomb: enable DDI0-DP port 2021-05-16 16:35:30 +00:00
northbridge nb/intel/gm45: Guard even more macro parameters 2021-05-16 21:53:36 +00:00
security vboot/secdata_tpm: Create FWMP space in coreboot 2021-05-16 21:54:24 +00:00
soc vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00 2021-05-16 22:17:26 +00:00
southbridge sb/intel: Drop outdated SMBus I/O BAR comment 2021-05-16 22:09:14 +00:00
superio src: Retype option API to use unsigned integers 2021-05-06 14:48:15 +00:00
vendorcode vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00 2021-05-16 22:17:26 +00:00
Kconfig