2ae188b292
vboot2 abtracts tpm storage as some 'secure' space. Thus, it's firmware's responsibility to handle vboot specific operations with tpm. This CL just copies related files from vboot_reference so that we can see how code was modified in the next CL. Note rollback_index.c/h were renamed to antirollback.c/h. TEST=none BUG=none Branch=none Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I1792a622058f70a8fcd3c4037547539ad2870420 Reviewed-on: https://chromium-review.googlesource.com/206462 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
138 lines
4.3 KiB
C
138 lines
4.3 KiB
C
/* This file is automatically generated */
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const struct s_tpm_extend_cmd{
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uint8_t buffer[34];
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uint16_t pcrNum;
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uint16_t inDigest;
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} tpm_extend_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x22, 0x0, 0x0, 0x0, 0x14, },
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10, 14, };
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const struct s_tpm_get_random_cmd{
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uint8_t buffer[14];
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uint16_t bytesRequested;
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} tpm_get_random_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xe, 0x0, 0x0, 0x0, 0x46, },
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10, };
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const struct s_tpm_getownership_cmd{
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uint8_t buffer[22];
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} tpm_getownership_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x5, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x11, },
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};
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const struct s_tpm_getpermissions_cmd{
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uint8_t buffer[22];
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uint16_t index;
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} tpm_getpermissions_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x11, 0x0, 0x0, 0x0, 0x4, },
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18, };
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const struct s_tpm_getstclearflags_cmd{
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uint8_t buffer[22];
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} tpm_getstclearflags_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x9, },
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};
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const struct s_tpm_getflags_cmd{
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uint8_t buffer[22];
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} tpm_getflags_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, 0x0, 0x1, 0x8, },
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};
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const struct s_tpm_physicalsetdeactivated_cmd{
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uint8_t buffer[11];
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uint16_t deactivated;
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} tpm_physicalsetdeactivated_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xb, 0x0, 0x0, 0x0, 0x72, },
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10, };
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const struct s_tpm_physicalenable_cmd{
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uint8_t buffer[10];
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} tpm_physicalenable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x6f, },
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};
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const struct s_tpm_physicaldisable_cmd{
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uint8_t buffer[10];
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} tpm_physicaldisable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x70, },
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};
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const struct s_tpm_forceclear_cmd{
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uint8_t buffer[10];
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} tpm_forceclear_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x5d, },
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};
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const struct s_tpm_readpubek_cmd{
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uint8_t buffer[30];
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} tpm_readpubek_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x1e, 0x0, 0x0, 0x0, 0x7c, },
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};
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const struct s_tpm_continueselftest_cmd{
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uint8_t buffer[10];
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} tpm_continueselftest_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53, },
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};
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const struct s_tpm_selftestfull_cmd{
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uint8_t buffer[10];
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} tpm_selftestfull_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x50, },
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};
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const struct s_tpm_resume_cmd{
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uint8_t buffer[12];
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} tpm_resume_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2, },
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};
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const struct s_tpm_savestate_cmd{
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uint8_t buffer[10];
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} tpm_savestate_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x98, },
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};
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const struct s_tpm_startup_cmd{
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uint8_t buffer[12];
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} tpm_startup_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x1, },
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};
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const struct s_tpm_finalizepp_cmd{
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uint8_t buffer[12];
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} tpm_finalizepp_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x2, 0xa0, },
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};
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const struct s_tpm_pplock_cmd{
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uint8_t buffer[12];
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} tpm_pplock_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x4, },
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};
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const struct s_tpm_ppenable_cmd{
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uint8_t buffer[12];
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} tpm_ppenable_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x20, },
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};
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const struct s_tpm_ppassert_cmd{
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uint8_t buffer[12];
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} tpm_ppassert_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x40, 0x0, 0x0, 0xa, 0x0, 0x8, },
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};
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const struct s_tpm_pcr_read_cmd{
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uint8_t buffer[14];
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uint16_t pcrNum;
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} tpm_pcr_read_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0xe, 0x0, 0x0, 0x0, 0x15, },
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10, };
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const struct s_tpm_nv_read_cmd{
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uint8_t buffer[22];
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uint16_t index;
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uint16_t length;
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} tpm_nv_read_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x16, 0x0, 0x0, 0x0, 0xcf, },
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10, 18, };
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const struct s_tpm_nv_write_cmd{
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uint8_t buffer[256];
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uint16_t index;
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uint16_t length;
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uint16_t data;
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} tpm_nv_write_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xcd, },
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10, 18, 22, };
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const struct s_tpm_nv_definespace_cmd{
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uint8_t buffer[101];
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uint16_t index;
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uint16_t perm;
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uint16_t size;
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} tpm_nv_definespace_cmd = {{0x0, 0xc1, 0x0, 0x0, 0x0, 0x65, 0x0, 0x0, 0x0, 0xcc, 0x0, 0x18, 0, 0, 0, 0, 0x0, 0x3, 0, 0, 0, 0x1f, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0, 0x3, 0, 0, 0, 0x1f, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x0, 0x17, },
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12, 70, 77, };
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const int kWriteInfoLength = 12;
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const int kNvDataPublicPermissionsOffset = 60;
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