coreboot/mainboard
Ronald G. Minnich e0031f798f I am well aware this does not compile :-)
But we can start to build it now. 

Add the serengeti. Now comes the fun part: trying to get it to build.

Be aware that things have changed. 
Stage1 is going to need to start up the APs, load the microcode, before we can event attempt to run initram. 

So we're going to need more sophisticated code than we've had in the past. 

Note also that copying cache_as_ram_auto.c and hacking it is NOT an option. We're going to have to 
recreate stage 1 and initram from scratch. I expect this to improve the code anyway. 

Signed-off-by: Ronald G. Minnich <rminnich@gmail.com
Acked-by: Ronald G. Minnich <rminnich@gmail.com



git-svn-id: svn://coreboot.org/repository/coreboot-v3@773 f3766cd6-281f-0410-b1cd-43a5c92072e9
2008-08-15 22:04:31 +00:00
..
adl Convert stage2 and initram makefile rules from object to source files. 2008-08-02 20:56:11 +00:00
amd I am well aware this does not compile :-) 2008-08-15 22:04:31 +00:00
artecgroup artecgroup/dbe62: Fix SPD_NUM_COLUMNS value (DIMM page size) 2008-08-13 17:21:09 +00:00
emulation CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE was never used. Kill 2008-08-15 16:41:37 +00:00
gigabyte arch/x86/pci_ops_conf1.c is already linked into stage1 and SHARED. 2008-08-15 19:56:41 +00:00
pcengines CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION_RAMSIZE was never used. Kill 2008-08-15 16:41:37 +00:00
Kconfig The m57sli almost builds. It's pretty empty. The dtc is not run . 2008-08-01 17:03:22 +00:00