3df6cc9de6
For GICD and GICR a SOC needs to implement 2 callbacks to get the base of those interrupt controllers. For all the cpu GIC the code loops over all the DEVICE_PATH_GICC_V3 devices in a similar fashion to how x86 lapics are added. It's up to the SOC to add those devices to the tree. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I5074d0a76316e854b7801e14b3241f88e805b02f Reviewed-on: https://review.coreboot.org/c/coreboot/+/76132 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> |
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| .. | ||
| acpi.c | ||
| acpi_apic.c | ||
| acpi_dmar.c | ||
| acpi_gic.c | ||
| acpi_hpet.c | ||
| acpi_pm.c | ||
| acpigen.c | ||
| acpigen_dptf.c | ||
| acpigen_dsm.c | ||
| acpigen_extern.asl | ||
| acpigen_pci.c | ||
| acpigen_ps2_keybd.c | ||
| acpigen_usb.c | ||
| device.c | ||
| dsdt_top.asl | ||
| fadt_filler.c | ||
| gnvs.c | ||
| Kconfig | ||
| Makefile.inc | ||
| pld.c | ||
| sata.c | ||
| soundwire.c | ||