92d77dd2e3
Use already defined macros in `spd.h`, ddr3.h`and `ddr4.h`. TEST=Built google/cyan (Cyan) with BUILD_TIMELESS=1, no change in output ROM. Change-Id: I727aa38236ad97f9c529389fdb7d7d11c1db08d0 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82314 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
46 lines
1.3 KiB
C
46 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef SPD_BIN_H
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#define SPD_BIN_H
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#include <stdint.h>
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#include <commonlib/region.h>
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#define SPD_PAGE_0 (0x6C >> 1)
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#define SPD_PAGE_1 (0x6E >> 1)
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#define SPD_DENSITY_BANKS 4
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#define SPD_ADDRESSING 5
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#define SPD_SN_LEN 4
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#define DDR3_ORGANIZATION 7
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#define DDR3_BUS_DEV_WIDTH 8
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#define DDR4_ORGANIZATION 12
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#define DDR4_BUS_DEV_WIDTH 13
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#define DDR4_SPD_SN_OFF 325
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struct spd_block {
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u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */
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u8 *spd_array[CONFIG_DIMM_MAX];
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/* Length of each dimm */
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u16 len;
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};
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void print_spd_info(uint8_t spd[]);
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uintptr_t spd_cbfs_map(u8 spd_index);
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void dump_spd_info(struct spd_block *blk);
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void get_spd_smbus(struct spd_block *blk);
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int spd_read_byte(u8 slave_addr, u8 bus_addr);
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int spd_read_word(u8 slave_addr, u8 bus_addr);
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void spd_write_byte(u8 slave_addr, u8 bus_addr, u8 value);
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/*
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* get_spd_sn returns the SODIMM serial number. It only supports DDR3 and DDR4.
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* return CB_SUCCESS, sn is the serial number and sn=0xffffffff if the dimm is not present.
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* return CB_ERR, if dram_type is not supported or addr is a zero.
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*/
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enum cb_err get_spd_sn(u8 addr, u32 *sn);
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/* expects SPD size to be 128 bytes, reads from "spd.bin" in CBFS and
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verifies the checksum. Only available if CONFIG_DIMM_SPD_SIZE == 128. */
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int read_ddr3_spd_from_cbfs(u8 *buf, int idx);
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#endif
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