Angel Pons c037695c19 sec/intel/txt/ramstage.c: Do not init the heap on S3 resume ... It causes problems on Haswell: SINIT detects that the heap tables differ in size, and then issues a Class Code 9, Major Error Code 1 TXT reset. Change-Id: I26f3d291abc7b2263e0b115e94426ac6ec8e5c48 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>		2020-10-22 20:02:58 +00:00
..
stm	security/intel/stm: Add options for STM build	2020-10-12 08:49:57 +00:00
txt	sec/intel/txt/ramstage.c: Do not init the heap on S3 resume	2020-10-22 20:02:58 +00:00
Kconfig	treewide: Remove "this file is part of" lines	2020-05-11 17:11:40 +00:00
Makefile.inc	security/intel/stm: Add STM support	2020-02-05 18:49:27 +00:00