coreboot/src/cpu/i786
Eric W. Biederman 0f7f76fb40 Hopefully this is my last commit of major infrasture changes for a while.
Highlights:
 - elfboot.c Now can load images to the ram location where linuxBIOS is running
 - Added the standalone directory for bootloaders built from the linuxBIOS source

Other things:
- Correctly maode fallback_boot.c conditional
- Added entry32.lds to do the math for segment descriptor table entries
- Merged ldscript.cacheram and ldscript.base
- Moved assembly code to the sections .rom.text and .rom.data
- Modified linuxBIOS so C code completely runs from RAM as the SiS630
  case does
- Updated and commented example config files for the supermicro p4dc6
- Bumped the elfboot loader version to 1.0
- Removed extra carriage returns in dump_northbridge.inc (DOS->UNIX)
- General cleanups to the config of the supermicro p4dc6
2002-01-16 05:54:23 +00:00
..
cache_ram.lds Hopefully this is my last commit of major infrasture changes for a while. 2002-01-16 05:54:23 +00:00
cache_ram_fini.inc Initial checkin for supermicro p4dc6 2001-11-03 02:11:49 +00:00
cache_ram_init.inc - Updates for the supermicro p4dc6 motherboard 2001-11-27 19:29:59 +00:00
cache_ram_start.inc Hopefully this is my last commit of major infrasture changes for a while. 2002-01-16 05:54:23 +00:00
Config Lots and Lots of changes. Mainly bugfixes for the supermicro p4dc6, 2001-12-20 04:04:42 +00:00
delay_i786.c Lots and Lots of changes. Mainly bugfixes for the supermicro p4dc6, 2001-12-20 04:04:42 +00:00
earlymtrr.inc Initial checkin for supermicro p4dc6 2001-11-03 02:11:49 +00:00