coreboot/src/soc/intel/skylake
Duncan Laurie bf7b5bc64a skylake: Work around issue in ACPI interpreter
There appears to be an issue that is causing this particular bit of
ACPI code to be incorrectly interpreted by the kernel and the IASL
disassembler.

Ensuring the PCRB() method is defined in the DSDT before any uses of
it appears to fix the problem, but that relies on specific ordering
of the ASL files included by pch.asl and may break again in the future
if the includes were re-ordered.  (they are alphabetic now)

So in this case to work around the issue unroll the function call so
the admittedly messy calculation is reduced to a constant when compiled.

Note this issue was observed with both iasl-20130117 and
iasl-20150717.

ACPICA bug: https://bugs.acpica.org/show_bug.cgi?id=1201

BUG=chrome-os-partner:45760
BRANCH=none
TEST=verify disassembled AML is correct

Change-Id: I7b6a3b792f79755db0ea7b9f2ef6ee7f5000e018
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ecacc340d6e1068ea649f0859657bb3208695730
Original-Change-Id: I232523f5b6ce290da6e7d99405a53b9437b10e0d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302167
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11721
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-28 09:35:52 +00:00
..
acpi skylake: Work around issue in ACPI interpreter 2015-09-28 09:35:52 +00:00
bootblock x86: bootblock: remove linking and program flow from build system 2015-09-09 03:22:58 +00:00
include/soc Skylake: update C state latency and power numbers 2015-09-17 14:19:32 +00:00
microcode microcode: Unify rules to add microcode to CBFS once again 2015-09-07 23:51:30 +00:00
romstage chromeos: vboot and chromeos dependency removal for sw write protect state 2015-09-23 19:35:31 +00:00
acpi.c skylake: Use common ACPI _SWS code 2015-09-17 14:23:40 +00:00
chip.c intel/skylake: Create "RtcLock" Silicon UPD from coreboot 2015-09-17 14:16:58 +00:00
chip.h intel/skylake: Create "RtcLock" Silicon UPD from coreboot 2015-09-17 14:16:58 +00:00
cpu.c skylake: only generate ACPI cpu entries once 2015-08-27 14:20:25 +00:00
cpu_info.c
elog.c skylake: align power management names with hardware 2015-07-29 19:31:07 +02:00
finalize.c
flash_controller.c skylake: refactor flash_controller code 2015-09-08 11:30:11 +00:00
gpio.c Skylake: Print GPIO MMIO base and pad config using gpio_debug token 2015-09-10 09:43:37 +00:00
igd.c skylake: igd: clean up igd.c 2015-09-08 11:48:21 +00:00
Kconfig skylake: Use common ACPI _SWS code 2015-09-17 14:23:40 +00:00
lpc.c skylake: correct IO-APIC redirection entry count 2015-08-19 14:04:08 +00:00
Makefile.inc fsp1_1: provide binding to UEFI version 2015-09-10 17:52:28 +00:00
memmap.c Skylake: update cbmem_top 2015-08-19 14:04:31 +00:00
monotonic_timer.c skylake: allow timer_monotonic_get() in all stages 2015-09-08 11:22:24 +00:00
pch.c
pcie.c
pcr.c skylake: provide pcr helper to get a port's register space 2015-07-29 19:30:49 +02:00
pei_data.c intel/skylake: Fix RMT disable of saved training data 2015-08-29 07:18:49 +00:00
pmc.c Skylake:Set DISB inside romstage after mrc init 2015-09-08 11:35:37 +00:00
pmutil.c skylake: fix SMI GPI status handling 2015-08-14 15:21:16 +02:00
ramstage.c fsp1_1: provide binding to UEFI version 2015-09-10 17:52:28 +00:00
smbus.c
smbus_common.c
smi.c
smihandler.c skylake: fix SMI GPI status handling 2015-08-14 15:21:16 +02:00
smmrelocate.c Skylake: update cbmem_top 2015-08-19 14:04:31 +00:00
systemagent.c Skylake: update cbmem_top 2015-08-19 14:04:31 +00:00
tsc_freq.c
uart.c skylake: fix serial port with new code base 2015-08-13 16:33:53 +02:00
uart_debug.c skylake: fix serial port with new code base 2015-08-13 16:33:53 +02:00
xhci.c