Also added comments.
A big change is in the dts. In OFW trees, the hierarchy seems to be:
/root/cpu/northbridge
south
other pci
note that the north is in the hierarchy under the south. This hierarchy
makes no sense on systems with a shared frontside bus, or at least I
don't see how it can. In those systems, it's easier to think about
the CPUs AND northbridges as children of the front side bus.
in LinuxBIOS, it has always been this:
/root/cpu/whatever
/root/northbridge/
south
other pci
There have been many discussions over how it ought to be, for 8 years
now, and we've always come back to how LB does it. So I have changed the
dts for qemu for now to match LB's way of doing things. Note that the
new system is flexible enough that, on K8, we CAN do things as above:
/cpu@0/amd8knorthbridge/etc.
/cpu@1/amd8knorthbridge/etc.
But on qemu, for now, the root is the mainboard, and the CPU and
northbridge are siblings.
I've added some informational printks, cleaned up pci_ops, and done
other things so that it builds and all seems to work -- until it hangs
hard in enumeration in i440bx ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://coreboot.org/repository/LinuxBIOSv3@160 f3766cd6-281f-0410-b1cd-43a5c92072e9
214 lines
6.8 KiB
C
214 lines
6.8 KiB
C
/*
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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//#include <part/hard_reset.h>
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/**
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* Read the resources for the root device,
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* that encompass the resources for the entire system.
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* @param root Pointer to the device structure for the system root device
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*/
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void root_dev_read_resources(struct device * root)
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{
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struct resource *resource;
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/* Initialize the system wide io space constraints */
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resource = new_resource(root, 0);
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resource->base = 0x400;
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resource->size = 0;
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resource->align = 0;
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resource->gran = 0;
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO;
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compute_allocate_resource(&root->link[0], resource,
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IORESOURCE_IO, IORESOURCE_IO);
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/* Initialize the system wide memory resources constraints */
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resource = new_resource(root, 1);
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resource->base = 0;
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resource->size = 0;
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resource->align = 0;
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resource->gran = 0;
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resource->limit = 0xffffffffUL;
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resource->flags = IORESOURCE_MEM;
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compute_allocate_resource(&root->link[0], resource,
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IORESOURCE_MEM, IORESOURCE_MEM);
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}
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/**
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* @brief Write the resources for every device
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*
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* Write the resources for the root device,
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* and every device under it which are all of the devices.
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* @param root Pointer to the device structure for the system root device
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*/
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void root_dev_set_resources(struct device * root)
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{
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struct bus *bus;
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bus = &root->link[0];
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compute_allocate_resource(bus,
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&root->resource[0], IORESOURCE_IO, IORESOURCE_IO);
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compute_allocate_resource(bus,
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&root->resource[1], IORESOURCE_MEM, IORESOURCE_MEM);
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phase4_assign_resources(bus);
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}
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/**
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* @brief Scan devices on static buses.
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*
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* The enumeration of certain buses is purely static. The existence of
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* devices on those buses can be completely determined at compile time
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* and is specified in the config file. Typical examples are the 'PNP'
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* devices on a legacy ISA/LPC bus. There is no need of probing of any kind,
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* the only thing we have to do is to walk through the bus and
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* enable or disable devices as indicated in the config file.
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*
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* On the other hand, some devices are virtual and their existence is
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* artificial. They can not be probed at run time. One example is the
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* debug device. Those virtual devices have to be listed in the config
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* file under some static bus in order to be enumerated at run time.
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*
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* This function is the default scan_bus() method for the root device and
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* LPC bridges.
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*
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* @param bus Pointer to the device structure which the static buses are attached
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* @param max Maximum bus number currently used before scanning.
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* @return Largest bus number used.
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*/
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static int smbus_max = 0;
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unsigned int scan_static_bus(struct device * busdevice, unsigned int max)
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{
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struct device * child;
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unsigned link;
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printk(BIOS_INFO, "%s for %s\n", __func__, dev_path(busdevice));
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for(link = 0; link < busdevice->links; link++) {
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/* for smbus bus enumerate */
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child = busdevice->link[link].children;
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if(child && child->path.type == DEVICE_PATH_I2C) {
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busdevice->link[link].secondary = ++smbus_max;
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}
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for(child = busdevice->link[link].children; child; child = child->sibling) {
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if (child->chip_ops && child->chip_ops->enable_dev) {
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child->chip_ops->enable_dev(child);
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}
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/* sigh. Have to enable to scan ... */
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if (child->ops && child->ops->phase5_enable_resources) {
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child->ops->phase5_enable_resources(child);
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}
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if (child->path.type == DEVICE_PATH_I2C) {
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printk(BIOS_DEBUG, "smbus: %s[%d]->",
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dev_path(child->bus->dev), child->bus->link );
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}
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printk(BIOS_DEBUG, "%s %s\n",
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dev_path(child),
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child->enabled?"enabled": "disabled");
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}
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}
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for(link = 0; link < busdevice->links; link++) {
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for(child = busdevice->link[link].children; child; child = child->sibling) {
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if (!child->ops || !child->ops->phase3_scan)
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continue;
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printk(BIOS_INFO, "%s scanning...\n", dev_path(child));
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max = dev_phase3_scan(child, max);
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}
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}
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printk(BIOS_INFO, "%s for %s done\n", __func__, dev_path(busdevice));
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return max;
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}
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/**
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* @brief Enable resources for children devices
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*
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* @param dev the device whos children's resources are to be enabled
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*
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* This function is called by the global enable_resource() indirectly via the
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* device_operation::enable_resources() method of devices.
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*
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* Indirect mutual recursion:
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* enable_childrens_resources() -> enable_resources()
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* enable_resources() -> device_operation::enable_resources()
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* device_operation::enable_resources() -> enable_children_resources()
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*/
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void enable_childrens_resources(struct device * dev)
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{
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unsigned link;
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for(link = 0; link < dev->links; link++) {
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struct device * child;
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for(child = dev->link[link].children; child; child = child->sibling) {
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dev_phase5(child);
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}
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}
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}
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void root_dev_enable_resources(struct device * dev)
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{
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enable_childrens_resources(dev);
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}
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/**
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* @brief Scan root bus for generic systems
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*
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* @param root The root device structure
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* @param max The current bus number scanned so far, usually 0x00
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*
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* This function is the default scan_bus() method of the root device.
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*/
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unsigned int root_dev_scan_bus(struct device * root, unsigned int max)
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{
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return scan_static_bus(root, max);
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}
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void root_dev_init(struct device * root)
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{
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}
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void root_dev_reset(struct bus *bus)
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{
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printk(BIOS_INFO, "Reseting board... NOT! Define hard_reset please\n");
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// hard_reset();
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}
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/**
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* @brief Default device operation for root device
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*
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* This is the default device operation for root devices. These operations
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* should be fully usable as is. However the chip_operations::enable_dev()
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* of a motherboard can override this if you want non-default behavior.
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*/
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struct device_operations default_dev_ops_root = {
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.phase4_read_resources = root_dev_read_resources,
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.phase4_set_resources = root_dev_set_resources,
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.phase5_enable_resources = root_dev_enable_resources,
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.phase6_init = root_dev_init,
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.phase3_scan = root_dev_scan_bus,
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.reset_bus = root_dev_reset,
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};
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/**
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* @brief The root of device tree.
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*
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* This is the root of the device tree. The device tree is defined in the
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* static.c file and is generated by config tool during compile time.
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*/
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extern struct device dev_root;
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