Furquan Shaikh bee831e958 soc/intel/tgl: Enable USB4 resources based on common Kconfig ... Intel TGL BIOS specification (doc ##611569) Revision 0.7.6 Section 7.2.5.1.5 recommends reserving the following resources for each PCIe USB4 root port: - 42 buses - 194 MiB Non-prefetchable memory - 448 MiB Prefetchable memory This change enables reserving of resources for USB4 when mainboard selects the newly added Kconfig SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES. This is similar to the change for ADL in commit 8d11cdc6fa ("soc/intel/alderlake: Add Kconfig for recommended PCIe TBT resources"). Change-Id: I25ec3f74ebd5727fa4b13f5a3b11050f77ecb008 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57125 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-09-13 22:42:55 +00:00
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amd	soc/amd/common/block/cpu: Add missing include	2021-09-13 14:17:15 +00:00
cavium	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
example	src: Introduce ARCH_ALL_STAGES_X86	2021-07-02 08:19:10 +00:00
intel	soc/intel/tgl: Enable USB4 resources based on common Kconfig	2021-09-13 22:42:55 +00:00
mediatek	mipi: Make panel init callback work directly on DSI transaction types	2021-09-11 01:42:47 +00:00
nvidia	mipi: Make panel init callback work directly on DSI transaction types	2021-09-11 01:42:47 +00:00
qualcomm	mipi: Make panel init callback work directly on DSI transaction types	2021-09-11 01:42:47 +00:00
rockchip	mipi: Make panel init callback work directly on DSI transaction types	2021-09-11 01:42:47 +00:00
samsung	commonlib/region: Turn addrspace_32bit into a more official API	2021-04-21 02:06:26 +00:00
sifive	memlayout: Store region sizes as separate symbols	2021-02-19 08:39:26 +00:00
ti	soc/ti/am335x/mmc.c: Fix memset length argument	2021-04-04 09:58:26 +00:00
ucb