coreboot/src
Icarus Chau be47636de0 broadcom/cygnus: Enable DDR auto self-refresh
Enable auto entry and auto exit self-refresh.
Configure entry idle time to 16x long count sequences.
Where a long count sequence is 1024 cycles.
The idle entry configuration is based on 32x of the DLL lock time (512 cycles).
A conservative setting to help minimize self-refresh enter/exit thrashing.

BUG=chrome-os-partner:36456
BRANCH=broadcom-firmware
TEST=When enable configuration CYGNUS_SDRAM_TEST_DDR,
print on console:

sdram initialization is completed.
test ddr start from 0x60000000 to 0x80000000
...
test ddr end: fail=0
Translation table is @ 02004000
Mapping address range [0x00000000:0x00000000) as uncached

Change-Id: Ibad220429fd52ead2933db03bec1a555f9385e53
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3768f82ca268fb854f8c4753916518a1efdf887d
Original-Reviewed-on: https://chrome-internal-review.googlesource.com/212125
Original-Reviewed-by: Scott Branden <sbranden@broadcom.com>
Original-Reviewed-by: Daisuke Nojiri <dnojiri@google.com>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@google.com>
Original-Tested-by: Daisuke Nojiri <dnojiri@google.com>
Original-Signed-off-by: Icarus Chau <ichau@broadcom.com>
Original-Change-Id: Icac1e12745d048b32e1804a546f6b49c8b5953c0
Original-Reviewed-on: https://chromium-review.googlesource.com/265862
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Trybot-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: http://review.coreboot.org/9930
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-04-22 09:03:46 +02:00
..
arch armv8/secmon: Disable and Enable GIC in PSCI path 2015-04-22 09:03:01 +02:00
console Add console wrapper for UART driver 2015-04-14 21:25:34 +02:00
cpu arm(64): Globally replace writel(v, a) with write32(a, v) 2015-04-21 08:22:28 +02:00
device device: Add class and subclass name support 2015-04-22 08:55:29 +02:00
drivers armv8/secmon: Disable and Enable GIC in PSCI path 2015-04-22 09:03:01 +02:00
ec chromeec: lpc: Add variant MEC IO 2015-04-22 08:58:13 +02:00
include armv8/secmon: Disable and Enable GIC in PSCI path 2015-04-22 09:03:01 +02:00
lib build system: add manual board id support 2015-04-22 08:56:46 +02:00
mainboard google/veyron_rialto: support the developer key GPIO 2015-04-22 09:03:10 +02:00
northbridge northbridge/amd/agesa/familyXY: Make NULL device op explicit 2015-04-09 19:34:22 +02:00
soc broadcom/cygnus: Enable DDR auto self-refresh 2015-04-22 09:03:46 +02:00
southbridge southbridge/intel/bd82x6x: Add LPC id 0x1e49 for B75 chipset 2015-04-20 23:51:34 +02:00
superio kconfig: drop intermittend forwarder files 2015-04-07 17:40:28 +02:00
vendorcode vboot: add mocked secdata 2015-04-22 09:01:19 +02:00
Kconfig build system: add manual board id support 2015-04-22 08:56:46 +02:00