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coreboot/src/arch/riscv
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Martin Roth 4635787895 src/arch: Fix checkpatch warning: no spaces at the start of a line 
Change-Id: Id9846ceb714dceaea12ea33ce2aa2b8e5bb6f4df
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-07-25 14:26:30 +00:00
..
include src/arch: Fix checkpatch warning: no spaces at the start of a line 2017-07-25 14:26:30 +00:00
boot.c riscv: start to use the configstring functions 2016-11-12 19:23:22 +01:00
bootblock.S riscv: get SBI calls to work 2017-01-16 00:26:08 +01:00
id.ld arch/riscv: Add missing license headers 2016-01-18 02:14:03 +01:00
id.S src/arch/riscv/id.S: Don't hardcode the strings 2016-08-04 17:17:38 +02:00
Kconfig riscv: start to use the configstring functions 2016-11-12 19:23:22 +01:00
Makefile.inc riscv: start to use the configstring functions 2016-11-12 19:23:22 +01:00
mcall.c riscv: Move mcall numbers to mcall.h, adjust their names 2017-01-16 06:15:53 +01:00
misc.c arch/riscv: Add missing license headers 2016-01-18 02:14:03 +01:00
payload.S riscv: change payload() to pass the config string pointer as arg0 2016-11-13 00:16:37 +01:00
prologue.inc
sbi.S src: change coreboot to lowercase 2017-06-07 12:09:15 +02:00
stages.c arch: remove stage_exit() 2016-02-11 23:12:06 +01:00
tables.c lib: add common write_tables() implementation 2016-04-21 20:49:05 +02:00
trap_handler.c src: change coreboot to lowercase 2017-06-07 12:09:15 +02:00
trap_util.S riscv: get SBI calls to work 2017-01-16 00:26:08 +01:00
virtual_memory.c riscv: enable counters via m[us]counteren 2016-12-20 00:10:33 +01:00