coreboot/src
Aseda Aboagye bd503978d4 mb/google/dedede: Configure CBI EEPROM WP
On dedede boards without Cr50, the CrOS Board Info (CBI) EEPROM write
protect signal is decoupled from the hardware write protect signal.
Instead, we'd like for it to mirror the software write protect status.
This commit simply checks the software write protect status of the SPI
flash and sets the CBI EEPROM write protect if it's enabled.  To prevent
changing the WP signal at run-time, the GPIO configuration is also
locked down after the level has been set.  If HW WP is deasserted, the
CBI EEPROM WP will be deasserted as well.

BUG=b:191189275,b:184592299
BRANCH=None
TEST=Build and flash lalala, disable SW WP by running `flashrom -p host
--wp-disable` from a root shell and verify that the GPIO is asserted
after a reboot.  Export the gpio via sysfs and verify that attempting to
change the value of the GPIO is futile. Enable SW WP via `flashrom -p
host --wp-enable` and reboot the DUT. Again, export the GPIO via sysfs
and verify that attempts to change the GPIO value are futile.

localhost ~ # iotools mem_read32 0xfd6e08d0
0x44000200
localhost ~ # cd /sys/class/gpio/
localhost /sys/class/gpio # echo 217 > export
localhost /sys/class/gpio # cd gpio217/
localhost /sys/class/gpio/gpio217 # echo out > direction
localhost /sys/class/gpio/gpio217 # cat value
0
localhost /sys/class/gpio/gpio217 # echo 1 > value
localhost /sys/class/gpio/gpio217 # cat value
1
localhost /sys/class/gpio/gpio217 # iotools mem_read32 0xfd6e08d0
0x44000200

Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Change-Id: Ic103037921ec7d2f96f86178675c11a3a1357d1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-19 00:08:20 +00:00
..
acpi ACPI: Refactor use of global and device NVS 2021-06-14 19:45:56 +00:00
arch arch/x86/include/arch/smp/mpspec: improve mp_bustype enum definition 2021-06-18 16:02:09 +00:00
commonlib nvs: Add Chrome OS NVS (CNVS) information to coreboot tables 2021-06-18 18:38:14 +00:00
console src/console/init.c: Make get_log_level static inline again 2021-06-15 16:12:52 +00:00
cpu soc/intel/common/block/smm: Add mainboard_smi_finalize 2021-06-19 00:06:41 +00:00
device device: Add helper function devfn_disable() 2021-06-17 06:48:45 +00:00
drivers intel/fsp2_0: Add FSP_ARRAY_LOAD macro 2021-06-18 06:03:16 +00:00
ec ec/google: Fix bad return value 2021-06-17 17:04:56 +00:00
include soc/intel/common/block/smm: Add mainboard_smi_finalize 2021-06-19 00:06:41 +00:00
lib nvs: Add Chrome OS NVS (CNVS) information to coreboot tables 2021-06-18 18:38:14 +00:00
mainboard mb/google/dedede: Configure CBI EEPROM WP 2021-06-19 00:08:20 +00:00
northbridge nb/intel/ironlake: Factor out common uncore ASL 2021-06-17 15:58:44 +00:00
security security/tpm/tspi: Reduce scope of tspi_init_crtm 2021-06-16 09:52:21 +00:00
soc soc/intel/common/block/smm: Add mainboard_smi_finalize 2021-06-19 00:06:41 +00:00
southbridge sb/intel/i82870: Use ioapic utility functions 2021-06-16 19:55:09 +00:00
superio
vendorcode vc/mediatek/mt8195: Match definition with declaration 2021-06-15 19:46:39 +00:00
Kconfig