e63620012c
The Microchip EC can share the SPI flash with the x86 host. Since
it boots first and does power sequencing, there's no problem with
concurrent access happening. Due to various vendor specific flash
layouts used on x86, the EC needs a pointer to it's own firmware.
The pointer resides at flash offset 0 and is read by MEC152x and
MEC1701 and MEC172x ECs, probably others as well.
The introduced tool generates the EC FW PTR at flash offset 0.
Allows to get rid of hand-crafted binary files (EC_SIG) being used
on AMD mainboards that hardcode the offset and must manually being
checked if those match the FMAP.
When there'll be additional firmware regions added it becomes
unconvienient to maintain those by hand.
Usage output:
Usage: ./util/mec152x/mec152xtool <rom-file> <command>
-h|--help
-f|--fmap_region_name
Command:
GEN_ECFW_PTR - Writes the ECFW PTR
Based on https://chromium.googlesource.com/chromiumos/platform/ec/+/08f5a1e6fc2c9467230444ac9b582dcf4d9f0068/chip/mchp/util/pack_ec_mec172x.py
Change-Id: I3b74c9f65643ad4437de29d4aed307b1a2b33286
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
77 lines
2.1 KiB
C
77 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <assert.h>
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#include <commonlib/bsd/compiler.h>
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#include <endian.h>
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#include <fmap.h>
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#include <stdio.h>
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#include "rom.h"
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#include "utils.h"
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/* Generate EC FW PTR. EC FW must be 256 byte aligned and has a CRC-8 checksum */
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static uint32_t gen_signature(uint32_t rom_offset)
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{
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uint32_t signature = rom_offset >> 8;
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uint8_t crc = crc8_itu((uint8_t *)&signature, 3);
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signature |= ((uint32_t)crc) << 24;
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return signature;
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}
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/**
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* @brief Write the EC FW pointer to the ROM
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* @param rom_file The filename of the ROM to update
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* The ROM must contain a valid FMAP
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* @param fmap_region_name FMAP region name containing the EC firmware
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* @return True on success
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*
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* On MEC15x1 the firmware resides in the shared x86 SPI flash. As the EC
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* boots first and does the power sequencing there's no concurrent access.
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* The EC expects to find a pointer to the FW at offset 0.
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*/
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bool rom_set_ec_fw_ptr(const char rom_file[], const char *fmap_region_name)
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{
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struct mem_range file = {0};
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bool ret = false;
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file = map_file(rom_file, true);
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if (file.start == NULL) {
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fprintf(stderr, "ERROR: Failed to load \"%s\"\n", rom_file);
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return false;
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}
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long fmap_offset = fmap_find(file.start, file.length);
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if (fmap_offset >= 0) {
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struct fmap *fmap = (void *)(file.start + fmap_offset);
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const struct fmap_area *area = fmap_find_area(fmap, fmap_region_name);
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if (area == NULL) {
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fprintf(stderr,
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"ERROR: Found FMAP without '%s' in \"%s\"\n\n",
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fmap_region_name, rom_file);
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printf("FMAP is:\n");
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fmap_print(fmap);
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goto error;
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}
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/* EC FW must be aligned */
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if (area->offset % 256) {
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fprintf(stderr,
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"ERROR: Region '%s' not aligned to 256 in \"%s\"\n",
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fmap_region_name, rom_file);
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goto error;
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}
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/* EC FW pointer resides at offset 0 */
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uint32_t *ec_fw_ptr = (uint32_t *)file.start;
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*ec_fw_ptr = htole32(gen_signature(area->offset));
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} else {
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fprintf(stderr, "ERROR: FMAP not found \"%s\"\n", rom_file);
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goto error;
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}
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ret = true;
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error:
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unmap_file(file);
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return ret;
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}
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