coreboot/src
Aaron Durbin bc5b557a81 baytrail: add more iosf access functions
There's a slew of ports required to initialize baytrail's
perf and power values. Therefore, add the necessary
functionality in the iosf module as well as the reg_script
library.

BUG=chrome-os-partner:24345
BRANCH=None
TEST=Built and booted.

Change-Id: Id45def82f9b173abeba0e67e4055f21853e62772
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179748
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5007
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10 06:31:00 +02:00
..
arch Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
console console: Fix UART selection prompt 2014-04-30 23:47:28 +02:00
cpu cougar_canyon2: Switch CPU/NB/SB to the shared FSP code 2014-05-09 21:36:12 +02:00
device Introduce stage-specific architecture for coreboot 2014-05-06 20:23:31 +02:00
drivers Intel FSP: add a shared set of functions for the FSP 2014-05-09 21:35:56 +02:00
ec baytrail: Basic DPTF framework 2014-05-09 05:42:52 +02:00
include reg_script: add reg_script_run_on_dev() 2014-05-10 06:30:43 +02:00
lib baytrail: add more iosf access functions 2014-05-10 06:31:00 +02:00
mainboard cougar_canyon2: Switch CPU/NB/SB to the shared FSP code 2014-05-09 21:36:12 +02:00
northbridge cougar_canyon2: Switch CPU/NB/SB to the shared FSP code 2014-05-09 21:36:12 +02:00
soc baytrail: add more iosf access functions 2014-05-10 06:31:00 +02:00
southbridge cougar_canyon2: Switch CPU/NB/SB to the shared FSP code 2014-05-09 21:36:12 +02:00
superio superio/serverengines/pilot: Avoid .c includes 2014-05-09 08:26:14 +02:00
vendorcode Declare get_write_protect_state() without ChromeOS 2014-05-08 16:25:30 +02:00
Kconfig Intel FSP: add a shared set of functions for the FSP 2014-05-09 21:35:56 +02:00