coreboot/src/northbridge
Uwe Hermann bc359473e2 Minor tweaks in the 440BX RAM init code (trivial).
Still hardcoded for Tyan S1846.

This slightly increases performance, but it's still pretty horrible.
Some RAM settings are causing a dramatically slow system (confirmed
by comparing memtest performance results of the proprietary BIOS
and our code). Haven't found the problem, yet.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2007-06-07 22:16:30 +00:00
..
amd Add missing license headers, minor cosmetic fixes in existing headers. 2007-05-22 10:12:49 +00:00
ibm Use the canonical name of the vendors/devices and the 2006-11-05 18:50:49 +00:00
intel Minor tweaks in the 440BX RAM init code (trivial). 2007-06-07 22:16:30 +00:00
motorola/mpc107 Fix some CHIP_NAME() entries to use canonical names. 2007-02-19 19:11:20 +00:00
via The attached patch sets the MA map type correctly for all DIMMs I was 2007-05-10 19:02:19 +00:00