coreboot/src
Kyösti Mälkki bbf013c38f nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash
CBFS could start from below 4MB, and should be cacheable for the
purpose of early microcode update and CBFS search for romstage file.

Change-Id: Ia2a1c6e5fdcc3201fafc8cf5c841cebbbf0b30c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4626
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15 15:27:33 +01:00
..
arch lib: Make log2() available in romstage on ARM, not just x86 2014-01-13 04:03:06 +01:00
console Remove sprintf 2014-01-10 18:08:31 +01:00
cpu nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash 2014-01-15 15:27:33 +01:00
device lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_content 2014-01-12 17:41:02 +01:00
drivers xpowers/axp209: Add helper to set voltages from devicetree config 2014-01-13 06:24:54 +01:00
ec acpi/ec: Add missing delays 2014-01-12 18:06:06 +01:00
include Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR 2014-01-15 15:26:48 +01:00
lib lib: Add log2 ceiling function 2014-01-14 14:14:46 +01:00
mainboard Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR 2014-01-15 15:26:48 +01:00
northbridge sandybridge: Allow skipping mrc.cache 2014-01-15 14:56:01 +01:00
southbridge ibexpeak / bd82x6x: Make SATA mode user-visible option. 2014-01-12 18:03:23 +01:00
superio superio: Uncomment the w83627uhg UART clock source initialization 2014-01-03 18:47:22 +01:00
vendorcode CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_file 2014-01-12 17:41:58 +01:00
Kconfig Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR 2014-01-15 15:26:48 +01:00