Wim Vervoorn 67117c3971 {drivers,soc}/intel/fsp1_1: Move chipset specific logo handling to SoC ... FSP logo handling used PcdLogoPtr and PcdLogoSize which are elements of the chipset specific FSP structures. Create soc_load_logo() which will pass the logo pointer and size. This function will call fsp_load_logo which will load the logo. BUG=NA TEST= Build and verified logo is displayed on Facebook FBG1701 Change-Id: I86943e64ca1ddd05e7e88fc6b882cfd33b98272e Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37791 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2019-12-20 17:50:28 +00:00
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apollolake	arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE	2019-12-19 19:31:08 +00:00
baytrail	arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE	2019-12-19 19:31:08 +00:00
braswell	{drivers,soc}/intel/fsp1_1: Move chipset specific logo handling to SoC	2019-12-20 17:50:28 +00:00
broadwell	arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE	2019-12-19 19:31:08 +00:00
cannonlake	{drivers,soc}/intel/fsp2_0: Move chipset specific logo handling to SoC	2019-12-19 17:49:38 +00:00
common	{nb,soc}: Replace min/max() with MIN/MAX()	2019-12-20 17:46:37 +00:00
denverton_ns	src: Remove unused 'include <arch/cpu.h>'	2019-12-19 05:58:50 +00:00
icelake	src/soc/intel: Remove unused <stdlib.h>	2019-12-19 05:41:08 +00:00
quark	{nb,soc}: Replace min/max() with MIN/MAX()	2019-12-20 17:46:37 +00:00
skylake	{nb,soc}: Replace min/max() with MIN/MAX()	2019-12-20 17:46:37 +00:00
tigerlake	soc/intel/tigerlake: Add required header files in pch.c	2019-12-19 17:49:13 +00:00
Kconfig	soc/intel/Kconfig: Load Tiger Lake SOC Kconfig	2019-12-11 11:37:45 +00:00