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coreboot/src/cpu
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Stefan Reinauer bb9dff5556 sandybridge: Correct reporting of cores and threads 
The reporting of cores and threads in the system was a bit
ambiguous. This patch makes it clearer.

Change-Id: Ia05838a53f696fbaf78a1762fc6f4bf348d4ff0e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1786
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-11-12 03:27:25 +01:00
..
amd AMD agesa: add enable cache at the end of disable_cache_as_ram 2012-11-02 21:04:28 +01:00
intel sandybridge: Correct reporting of cores and threads 2012-11-12 03:27:25 +01:00
via VIA Nano: Add support for VIA Nano CPUs 2012-09-05 03:43:02 +02:00
x86 Synchronize rdtsc instructions 2012-08-09 00:38:39 +02:00
Kconfig buildsystem: Make CPU microcode updating more configurable 2012-09-05 03:40:47 +02:00
Makefile.inc buildsystem: Make CPU microcode updating more configurable 2012-09-05 03:40:47 +02:00