Subrata Banik baf922c798 soc/intel/common: Calculate and configure SF Mask 1 ... MSR IA_SF_QOS_INFO (0xc87) has been introduced since TGL and is used to find out the NUM_SNOOP_FILTER_WAYS. Bit[5:0] of MSR 0xc87 indicates the maximum number of bits that may be set in any of the SF MASK register. Hence, this patch calculates SF way count using below logic: Calculate SF masks 1: 1. Calculate SFWayCnt = (MSR 0xC87) & 0x3f 2. if CONFIG_SF_MASK_2WAYS_PER_BIT: a. SFWayCnt = SFWayCnt / 2 3. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - SF_MASK_2 Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-08-15 06:58:36 +00:00
..
acpi	Move post_codes.h to commonlib/console/	2021-08-04 15:15:51 +00:00
basecode
block	soc/intel/common: Calculate and configure SF Mask 1	2021-08-15 06:58:36 +00:00
pch	soc/intel/common: Add InSMM.STS support	2021-06-21 08:26:41 +00:00
fsp_reset.c
hda_verb.c
hda_verb.h
Kconfig.common
Makefile.inc
mma.c	intel: mma: Use new CBFS API	2021-04-14 01:03:33 +00:00
mma.h	intel: mma: Use new CBFS API	2021-04-14 01:03:33 +00:00
nhlt.c
reset.c
reset.h
smbios.c	device/dram/ddr3: Rename DDR3 SPD memory types	2021-04-05 13:01:37 +00:00
smbios.h
tpm_tis.c
vbt.c
vbt.h