Werner Zeh bab5d5008b soc/intel/elkhartlake: Expose In-Band ECC config to mainboard ... Elkhart Lake provides a feature called "In-Band ECC" which uses a piece of system DRAM to store the ECC information in. There are a few parameters in FSP-M to set this feature up as needed. This patch adds code to expose these parameters to the devicetree so that they can be configured on mainboard level as needed. Change-Id: I7a4953d7b35277de01daff04211450e3d1bd8103 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55668 Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-06-21 05:35:58 +00:00
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alderlake	soc/intel/alderlake: Add TBT PCIe root ports enablement	2021-06-18 21:42:35 +00:00
apollolake	soc/intel/apollolake: Make use of is_devfn_enabled() function	2021-06-16 03:47:46 +00:00
baytrail	ACPI: Refactor use of global and device NVS	2021-06-14 19:45:56 +00:00
braswell	ACPI: Refactor use of global and device NVS	2021-06-14 19:45:56 +00:00
broadwell	arch/x86/ioapic: Drop irq_on_fsb as a configurable item	2021-06-16 19:54:49 +00:00
cannonlake	soc/intel/cannonlake: Make use of is_devfn_enabled() function	2021-06-16 03:48:29 +00:00
common	soc/intel/common/block/cse: Move enum csme_failure_reason	2021-06-21 05:29:11 +00:00
denverton_ns	arch/x86/ioapic: Drop irq_on_fsb as a configurable item	2021-06-16 19:54:49 +00:00
elkhartlake	soc/intel/elkhartlake: Expose In-Band ECC config to mainboard	2021-06-21 05:35:58 +00:00
icelake	cpu/x86: Default to PARALLEL_MP selected	2021-06-07 21:02:54 +00:00
jasperlake	soc/intel/jasperlake: Add offsets for pad locking	2021-06-19 00:04:19 +00:00
quark	mainboards: Drop PWRS from GNVS	2021-02-11 16:35:32 +00:00
skylake	cpu/x86: Default to PARALLEL_MP selected	2021-06-07 21:02:54 +00:00
tigerlake	soc/intel/{alderlake,tigerlake}: Fix typo in pmc.h	2021-06-17 15:59:29 +00:00
xeon_sp	soc/intel/xeon_sp/cpx: Move MSR Locks to CPU init and fix them	2021-06-16 04:18:36 +00:00
Kconfig