coreboot/src/cpu
efdesign98 84cbce2364 Update AMD F14 Agesa to support Rev C0 cpus
This change updates the AMD Agesa code to support the Family 14
rev C0 cpus.  It also fixes (again) a ton of warnings, although
not all of them are gone.  The warning fixes affect code in the
Family 12 tree as well, so there are some small changes therein.
This code has been tested on a Persimmon and passes Abuild.
This is the first (and largest) of a number of commits to complete
the upgrade.

Change-Id: Id28d9bf7931f8baa2a602f6bb096a5a465ccd20d
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/131
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-08-06 18:06:18 +02:00
..
amd Update AMD F14 Agesa to support Rev C0 cpus 2011-08-06 18:06:18 +02:00
intel cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. 2011-08-04 08:10:12 +02:00
via more ifdef -> if fixes 2011-04-21 20:45:45 +00:00
x86 Add SSE3 dependent code 2011-07-22 08:22:59 +02:00
Kconfig - Fix shortcoming in Kconfig when handling multiple "choice"s 2010-12-16 23:37:17 +00:00
Makefile.inc qemu: drop "northbridge.c" from src/cpu/... 2010-03-29 21:17:25 +00:00