Jonathan Neuschäfer b8e67acc91 arch/riscv: Change all eret instructions to .word 0x30200073 (mret) ... Using the opcode directly is necessary for the transition to the GCC 6.1.0 based toolchain, because the old toolchain only supports eret and the new toolchain only supports mret. Change-Id: I17e14d4793ae5259f7ce3ce0211cbb27305506cc Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15290 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2016-07-18 22:50:33 +02:00
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acpi	arch/x86: provide common Intel ACPI hardware definitions	2016-07-15 08:31:21 +02:00
arch	arch/riscv: Change all eret instructions to .word 0x30200073 (mret)	2016-07-18 22:50:33 +02:00
commonlib	region: Add writeat and eraseat support	2016-06-24 20:48:12 +02:00
console	console/post: be explicit about conditional cmos_post_log() compiling	2016-05-25 18:04:11 +02:00
cpu	AMD binaryPI: Use common romstage ram stack	2016-07-15 12:31:07 +02:00
device	device: i2c: Add support for I2C bus operations	2016-06-09 17:05:40 +02:00
drivers	elog: Use rdev_mmap to find offset of ELOG	2016-07-18 08:12:12 +02:00
ec	ec/google/chromeec: provide common SMI handler helpers	2016-07-15 08:35:29 +02:00
include	lib: add poweroff() declaration	2016-07-15 08:35:15 +02:00
lib	AGESA: Use common romstage ram stack	2016-07-15 12:18:54 +02:00
mainboard	google/oak & elm: initialize touchscreen reset gpio	2016-07-18 20:14:29 +02:00
northbridge	intel/x4x: Do not use scratchpad register for ACPI S3	2016-07-15 16:57:57 +02:00
soc	gru: implement hw reset function	2016-07-18 20:14:07 +02:00
southbridge	southbridge/intel/fsp_bd82x6x: use common Intel ACPI hardware definitions	2016-07-15 08:34:46 +02:00
superio	sio/winbond/w83667hg-a: Add pinmux defines for UART B	2016-05-29 19:34:54 +02:00
vendorcode	chromeos: Fill in the firmware id (RO, RW A, RW B) FMAP sections	2016-07-15 00:40:19 +02:00
Kconfig	Romstage spinlocks require EARLY_CBMEM_INIT	2016-07-10 04:03:31 +02:00