Mike Wiitala b7eb1097e5 mb/g/drallion: Remove Wilco 1.0 CML variants from drallion code ... Remove the sarien_cml and arcada_cml subdirectories from the drallion/variants directory. BUG=b:140068267 TEST=./build_packages --board=drallion Confirm that drallion still builds successfully. BRANCH=none Change-Id: I9648965ca222d4d68bf73738716ad1c93739b03f Signed-off-by: Mike Wiitala <mwiitala@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org>		2019-12-16 09:36:40 +00:00
..
acpi
arch	bootblock: Provide some common prototypes	2019-12-14 14:08:57 +00:00
commonlib	printf: Automatically prefix %p with 0x	2019-12-11 11:38:59 +00:00
console	printf: Automatically prefix %p with 0x	2019-12-11 11:38:59 +00:00
cpu	bootblock: Provide some common prototypes	2019-12-14 14:08:57 +00:00
device	printf: Automatically prefix %p with 0x	2019-12-11 11:38:59 +00:00
drivers	drivers/mrc_cache: Redo indenting	2019-12-15 16:47:36 +00:00
ec
include	soc/intel/common: Add PCI device IDs for CMP-H	2019-12-13 09:05:20 +00:00
lib	fmap: Make FMAP_CACHE mandatory if it is configured in	2019-12-11 11:42:26 +00:00
mainboard	mb/g/drallion: Remove Wilco 1.0 CML variants from drallion code	2019-12-16 09:36:40 +00:00
northbridge	Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID"	2019-12-14 15:38:16 +00:00
security	security/vboot: Ensure firmware body size is respected again	2019-12-13 20:14:26 +00:00
soc	Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID"	2019-12-14 15:38:16 +00:00
southbridge	Revert "{northbridge,soc,southbridge}: Don't use both of _ADR and _HID"	2019-12-14 15:38:16 +00:00
superio	mb/msi/ms7721: Don't rewrite pnp_{enter,exit}_conf_state function	2019-12-15 11:54:54 +00:00
vendorcode	vc/amd/pi: Fix typo	2019-12-12 16:14:09 +00:00
Kconfig