coreboot/src
Kyösti Mälkki b6fc727903 FSP1_0 does not support HAVE_ACPI_RESUME
FSP1_0 places romstage ram stack at fixed location of
RAMTOP in low memory before returning to coreboot proper.
There is no possibility of making a complete backup of
RAMBASE..RAMTOP region and currently such backup is not
even attempted.

As a conclusion, S3 resume would always cause OS memory
corruption.

Change-Id: I5b9dd4069082e022b01b0d6a9ad5dec28a06e8b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15576
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-13 18:35:03 +02:00
..
acpi acpi/: add missing license header 2016-01-14 22:52:11 +01:00
arch acpi: Change device properties to work as a tree 2016-07-08 17:21:26 +02:00
commonlib region: Add writeat and eraseat support 2016-06-24 20:48:12 +02:00
console console/post: be explicit about conditional cmos_post_log() compiling 2016-05-25 18:04:11 +02:00
cpu intel post-car: Consolidate choose_top_of_stack() 2016-07-10 11:16:07 +02:00
device device: i2c: Add support for I2C bus operations 2016-06-09 17:05:40 +02:00
drivers tpm: report firmware version 2016-07-12 00:26:42 +02:00
ec google/chromeec: Update EC command header 2016-07-10 03:54:07 +02:00
include SPD: Add CAS latency 2 2016-07-12 15:17:31 +02:00
lib lib/selfboot: clear BSS segments 2016-07-12 23:39:14 +02:00
mainboard FSP1_0 does not support HAVE_ACPI_RESUME 2016-07-13 18:35:03 +02:00
northbridge nb/intel/x4x: Fix underclocking of 800MHz DDR2 RAM 2016-07-09 13:49:00 +02:00
soc Documentation: Fix doxygen errors 2016-07-12 22:41:02 +02:00
southbridge Documentation: Fix doxygen errors 2016-07-12 22:41:02 +02:00
superio sio/winbond/w83667hg-a: Add pinmux defines for UART B 2016-05-29 19:34:54 +02:00
vendorcode vboot2: tpm2 factory initialization. 2016-07-12 00:27:27 +02:00
Kconfig Romstage spinlocks require EARLY_CBMEM_INIT 2016-07-10 04:03:31 +02:00