Felix Held b6bb0c88be vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping table ... Sabrina only supports PCIe and no SATA or 10 GBit/s ethernet on its DXIO lanes. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib5aa3abf21e20bbe846f1acfdc2755e97eca1e63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63121 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2022-03-27 15:16:17 +00:00
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amd	vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping table	2022-03-27 15:16:17 +00:00
cavium	src: use ARRAY_SIZE where possible	2021-02-15 11:30:40 +00:00
eltan	vc/eltan/security/verified_boot/Makefile: add fmap_config.h dependency	2022-02-22 15:56:03 +00:00
google	vc/google/chromeos/Kconfig: Fix typo	2022-03-09 15:38:45 +00:00
intel	vendorcode/intel/edk2/edk2-stable202111: Use fixed size struct elements	2022-03-18 18:41:42 +00:00
mediatek	vc/mediatek/mt8195: Fix rank1 CKE setting for single-rank DRAM	2021-12-01 09:48:17 +00:00
siemens	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
Makefile.inc	soc/mediatek/mt8192: initialize DRAM using vendor reference code	2021-03-08 03:15:43 +00:00