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coreboot/src/cpu/intel
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Arthur Heymans 67031a565b cpu/intel/sandybridge: Put stage cache into TSEG 
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.

The code is mostly copied from src/cpu/intel/haswell.

TESTED on Thinkpad X220: on a cold boot the stage cache gets created
and on S3 the cached ramstage gets properly used.

Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-10 09:30:21 +00:00
..
car cpu/intel/car/cache_as_ram.inc: Fix long standing issues 2017-09-12 07:54:59 +00:00
common cpu/intel/speedstep: Fix the PNOT ACPI method 2018-01-17 17:09:13 +00:00
fit
fsp_model_206ax Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
fsp_model_406dx Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
haswell cpu/intel/haswell: Don't select PARALLEL_CPU_INIT 2018-02-06 15:30:06 +00:00
hyperthreading
microcode
model_6bx Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
model_6dx Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
model_6ex intel: Replace msr(0x198) with msr(IA32_PERF_STATUS) 2017-11-30 17:21:17 +00:00
model_6fx intel: Replace msr(0x198) with msr(IA32_PERF_STATUS) 2017-11-30 17:21:17 +00:00
model_6xx Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
model_65x Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
model_67x Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
model_68x Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
model_69x Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
model_106cx Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
model_206ax cpu/intel/sandybridge: Put stage cache into TSEG 2018-04-10 09:30:21 +00:00
model_1067x Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
model_2065x intel/nehalem post-car: Use postcar_frame for MTRR setup 2018-04-09 12:03:58 +00:00
model_f2x Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
model_f3x Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
model_f4x Constify struct cpu_device_id instances 2017-11-23 05:00:17 +00:00
slot_1 cpu/intel/slot_1: Increase CAR size to 8KiB 2017-09-12 08:07:25 +00:00
slot_2
smm/gen1 cpu/intel/sandybridge: Put stage cache into TSEG 2018-04-10 09:30:21 +00:00
socket_441
socket_BGA956
socket_BGA1284
socket_FC_PGA370
socket_FCBGA559
socket_FCBGA1023 cpu/intel: Add Intel FCBGA1023 socket support 2017-11-07 04:39:14 +00:00
socket_LGA775
socket_LGA1155
socket_mFCPGA478
socket_mPGA478
socket_mPGA478MN
socket_mPGA604
socket_PGA370
socket_rPGA988B
socket_rPGA989
speedstep cpu/intel/speedstep: Fix the PNOT ACPI method 2018-01-17 17:09:13 +00:00
thermal_monitoring
turbo
Kconfig Intel i5000 board & chips: Remove - using LATE_CBMEM_INIT 2018-01-15 23:24:53 +00:00
Makefile.inc Intel i82830 boards & chips: Remove - using LATE_CBMEM_INIT 2018-01-15 23:25:26 +00:00