coreboot/src
Kyösti Mälkki b5a8a13bde pcengines/apu1: Fix 0:15.x PCIe root ports
Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done
to only advertise x1 lane width for PCIe link 0:15.0.

Hide functions of PCIe links that have no slots connected. Our PCI
infrastructure does not support bridge devices that are set off
in devicetree but remain visible in the PCI hardware tree.

Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8388
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-02-23 21:36:21 +01:00
..
arch Remove */cpu/amd/agesa/* from excluded illegal globals file 2015-02-23 10:39:43 +01:00
console CBMEM console: Fix and enhance pre-RAM support 2015-01-27 22:44:17 +01:00
cpu AMD Fam10h: Don't write uninitialized data into ACPI 2015-02-23 20:33:45 +01:00
device device/device_util.c: Add space after ellipse for better legibility 2015-02-15 09:21:09 +01:00
drivers drivers/xgi: Avoid double-free 2015-02-23 20:33:38 +01:00
ec acpi: Generate valid ACPI processor objects 2015-02-16 21:02:30 +01:00
include AMD K8 fam10: Refactor offset_unitid configuration 2015-02-20 07:04:00 +01:00
lib x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer 2015-02-15 08:50:22 +01:00
mainboard pcengines/apu1: Fix 0:15.x PCIe root ports 2015-02-23 21:36:21 +01:00
northbridge AMD binaryPI: Drop HT3_SUPPORT 2015-02-20 07:56:09 +01:00
soc tegra132: Postprocess bootblock properly 2015-02-17 18:11:01 +01:00
southbridge AMD cimx/sb800: Disconnect PCI bridge 0:14.4 from pins 2015-02-23 21:33:55 +01:00
superio superio/fintek/f81216h: Add the correct unlock key values 2015-02-14 00:53:26 +01:00
vendorcode AMD cimx/sb800: Disable unused GPP ports 2015-02-14 22:37:33 +01:00
Kconfig nvram: Add option to reset NVRAM to default parameters on every boot 2015-02-16 08:36:37 +01:00